Tadpole SPARCbook 3 series, Reference Manual

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7-4
PCMCIA Interface
TS102 Memory Mapping
port status register, and also asserts an interrupt request to the
microcontroller. The microcontroller read of the receive register clears the
CPU write busy bit and the interrupt request.
There is a similar protocol for transfers from the microcontroller to the
CPU. For improved performance, there is a four entry FIFO in each
direction, which allows posted write cycles to be performed.
7.2 TS102 Memory Mapping
The TS102 occupies a 256 Mbyte region of the SPARCbook 3’s address
space. Its internal memory map is summarized in Table 8-4.
7.2.1 Acceses to PCMCIA Resources
The low order SBus address lines S_A(25:0) are passed directly through to
PCM_A(25:0), permitting access to the full 64Mbyte of common memory
address space. For attribute memory and I/O space, PCM_A(25:24) are
driven from paging bits in the TS102’s register set.
The TS102 accepts byte, halfword, word, doubleword, quadword, and
octalword transfer requests, and responds with error acknowledgment on
request for other sizes.
The TS102 detects the WAIT signal from any card that drives it. This can
be used to extend the transfer cycle on memory and I/O accesses. The wait
can be asserted for up to 12
µ
s which is longer than the maximum 255 SBus
clocks (10.2
µ
s @ 25MHz) allowed for an SBus transfer. If a PCMCIA card
Address Resource
0x40000000 - 0x41FFFFFF FCode PROM
0x42000000 - 0x43FFFFFF TS102 registers
0x44000000 - 0x44FFFFFF Attribute space, card A
0x45000000 - 0x45FFFFFF Attribute space, card B
0x46000000 - 0x46FFFFFF I/O space, card A
0x47000000 - 0x47FFFFFF I/O space, card B
0x48000000 - 0x4BFFFFFF Common memory space, card A
0x4C000000- 0x4FFFFFFF Common memory space, card B
Table 7-1 TS102 Address map
S3GX_TRMBook Page 4 Friday, September 19, 1997 11:39 am