Tadpole SPARCbook 3 series, Reference Manual

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ISDN and 16-bit Audio
8-7
DBRI Overview
Fixed I/0 Channels S and Q channels are supported on the basic rate interfaces. They can be
connected to short data pipes, the other ends of which are in fixed I/O mode.
Commands set a value for S and Q which is output repeatedly until
changed. If an incoming S or Q channel changes, the change is reported on
the interrupt queue. Note that when receiving fixed data, the FXDT
interrupt reports only the least. significant 20 bits.
Frame Synchronization The DBRI TE interface always synchronizes to its receive signal (from the
network). The CHI can be either a slave or a master. If the CHI is master,
it generates CHICK and CHIFS, and synchronizes these to the TE interface,
if active. In CHI slave mode, the CHI synchronizes to the CHIFS input. If
the TE interface is also active, data transmission between the CHI and the
network can be unreliable. If the TE interface is synchronized with the
network before the NT interface or CHI is active, then the NT CHI is
frequency-locked with the TE when it is activated. It is recommended for
data transfer between TE and CHI that TE is activated first. In this way, all
interfaces are synchronized to TE and the network.
The DBRI provides a number of registers through which it is initialized,
and a command set through which it is, mostly, controlled. Initialization
performed by writing to the internal registers and command sequences are
started by writing to REG8.
8.2.5 DBRI Internal Registers
The DBRI provides six registers through which its operations can be
controlled. These are shown in Table 10-3.
Address
Registe
r
Function
0x50000000 - 3F ID Code Read-only FCode
0x50000040 REG0 Status and Control Register
0x50000044 REG1 Mode and Interrupt Control Register
0x50000048 REG2 Parallel I/O Register
0x5000004C REG3 Test Register
0x50000060 REG8 Command Queue Pointer
0x50000064 REG9 Interrupt Queue Pointer
Table 8-1 DBRI Internal Registers
S3GX_TRMBook Page 7 Friday, September 19, 1997 11:39 am