Tadpole SPARCbook 3 series, Reference Manual

Page: 158 / 216

11-8
Display Interface
Power 9100 User Interface Controller
Status and control
registers and
commands The Power 9100 contains a number of registers which are used to control
device operations. They are used, for example, to enable and handle
interrupts, to control parameter and drawing engine operations and to
configure video and VRAM operations.
In addition status and control registers, this area of the Power 9100’s host
interface provides several write-only or read-only locations which are
accessed to generate commands (i.e., it is the address that is interpreted as
the command). In the case of write commands, any data required to execute
the command is written to the command location.
Table 11-2 lists the addresses of the internal register sets and command
locations.
These registers are described briefly on the following pages. However, for
a detailed description of the Power 9100’s registers and capabilities, please
refer to the Power 9100 data book, see Appendix A, “Further Information”.
Base Address Register/Command Type Access
38000000 System Control Registers R/W
38000100 Video Control Registers R/W
38000180 VRAM Control Registers R/W
38000200 RAMDAC Control R/W
38000400 Video Coprocessor Interface R/W
38002000 Parameter Engine Status Register R
38002004 Blit Command R
38002008 Quad Command R
3800200C Pixel8 Command (Power9000 Format) W
38002014 Next_pixels Command W
38002080 Pixel1 Command W
38002180 Parameter Engine Registers R/W
38002200 Drawing Engine Pixel Processing Registers R/W
38003000 Device Coordinate Registers R/W
38003200 Load Coordinate Commands R/W
38004xxxx Pixel8 Command (Power 9100 Format) W
38800000 Frame Buffer Memory R/W
Table 11-2 Power 9100 Register Locations
S3GX_TRMBook Page 8 Friday, September 19, 1997 11:39 am