Tadpole SPARCbook 3 series, Reference Manual

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SCSI Controller
5-7
DMA Support
5.3 DMA Support
The SCSI controller is provided with DMA support by one channel of the
MACIO integral DMA controller. Between the FSC and Sbus the MACIO
provides a 64-byte deep FIFO (D-FIFO) which is bypassed by CPU
accesses to the FSC’s registers.
5.3.1 DMA Transfers
A transfer from SCSI to memory is carried out in two phases. First from the
SCSI controller to the DMA controller, and then from the DMA controller
to memory. Similarly, transfers from memory to SCSI are composed of a
transfer into the D-FIFO, and then a transfer between the D-FIFO and SCSI
controller.
Data from the SCSI is written into the D-FIFO until the largest possible
Sbus burst write, as specified in the DMA Controller’s Control and Status
register, to memory can be carried out.
5.3.2 DMA Registers
The DMA controller provides four 32-bit registers used to control DMA
operations with the FSC.
5.3.3 SCSI Interrupts
The SCSI controller signals interrupts to the CPU via the SLAVIO
multifunction peripheral on level 4. The interrupt service routine can
establish the cause of the interrupt by examining the contents of first the
status register, and then the interrupt status register.
Address Register Size Access
0x78400000 Control and Status Register 32 R/W
0x78400004 Address Register 32 R/W
0x78400008 Byte Count Register 24 R/W
0x7840000C Test Control and Status Register 32 R/W
Table 5-3 SCSI Related DMA Registers
S3GX_TRMBook Page 7 Friday, September 19, 1997 11:39 am