Renesas ZTAT H8S/2357F, Hardware Manual

Page: 901 / 1047

Rev.6.00 Oct.28.2004 page 873 of 1016
REJ09B0138-0600H
BCRL—Bus Control Register L H'FED5 Bus Controller
7
BRLE
0
R/W
6
BREQOE
0
R/W
5
EAE
1
R/W
4
LCASS
1
R/W
3
DDS
1
R/W
0
WAITE
0
R/W
2
—
1
R/W
1
WDBE
0
R/W
Bit
Initial value
Read/Write
:
:
:
Bus Release Enable
0
1
External bus release is disabled
External bus release is enabled
BREQO Pin Enable
0
1
BREQO output disabled
BREQO output enabled
0
1
On-chip ROM
External addresses (in external expansion mode)
or reserved area
*
2
(in single-chip mode)
Reserved
Only 1 should be written to this bit
External Addresses H'010000 to H'01FFFF
*
1
Enable
Write Data Buffer Enable
0
1
WAIT Pin Enable
0
1
Wait input by WAIT pin disabled
Wait input by WAIT pin enabled
Write data buffer function not used
Write data buffer function used
LCAS Select
Write 0 to this bit when using the DRAM interface
Notes: 1. External addresses H'010000 to H'01FFFF for the H8S/2357
External addresses H'010000 to H'03FFFF for the H8S/2398
2. Do not access a reserved area.
DACK Timing Select
When DMAC single address transfer is performed in
DRAM/PSRAM space, full access is always executed
DACK signal goes low from T
r
or T
1
cycle
0
1
Burst access is possible when DMAC single address
transfer is performed in DRAM/PSRAM space
DACK signal goes low from T
c1
or T
2
cycle