Renesas ZTAT H8S/2357F, Hardware Manual

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Rev.6.00 Oct.28.2004 page 423 of 1016
REJ09B0138-0600H
11.3 Operation
11.3.1 Overview
PPG pulse output is enabled when the corresponding bits in P1DDR, P2DDR, and NDER are set to 1. In this state the
corresponding PODR contents are output.
When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to
update the output values.
Figure 11-2 illustrates the PPG output operation and table 11-3 summarizes the PPG operating conditions.
Output trigger signal
Pulse output pin
Internal data bus
Normal output/inverted output
C
PODR Q D
NDER
Q
NDR Q D
DDR
Figure 11-2 PPG Output Operation
Table 11-3 PPG Operating Conditions
NDER DDR Pin Function
0 0 Generic input port
1 Generic output port
1 0 Generic input port (but the PODR bit is a read-only bit, and when
compare match occurs, the NDR bit value is transferred to the PODR bit)
1 PPG pulse output
Sequential output of data of up to 16 bits is possible by writing new output data to NDR before the next compare match.
For details of non-overlapping operation, see section 11.3.4, Non-Overlapping Pulse Output.