Renesas ZTAT H8S/2357F, Hardware Manual

Page: 445 / 1047

Rev.6.00 Oct.28.2004 page 417 of 1016
REJ09B0138-0600H
Address H'FF4E
Bit : 7 6 5 4 3 2 1 0
— — — — — — — —
Initial value : 1 1 1 1 1 1 1 1
R/W : — — — — — — — —
If pulse output groups 0 and 1 are triggered by the same compare match event, the NDRL address is H'FF4D. The upper 4
bits belong to group 1 and the lower 4 bits to group 0. Address H'FF4F consists entirely of reserved bits that cannot be
modified and are always read as 1.
Address H'FF4D
Bit : 7 6 5 4 3 2 1 0
NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
Address H'FF4F
Bit : 7 6 5 4 3 2 1 0
— — — — — — — —
Initial value : 1 1 1 1 1 1 1 1
R/W : — — — — — — — —
Different Triggers for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by different compare match
events, the address of the upper 4 bits in NDRH (group 3) is H'FF4C and the address of the lower 4 bits (group 2) is
H'FF4E. Bits 3 to 0 of address H'FF4C and bits 7 to 4 of address H'FF4E are reserved bits that cannot be modified and are
always read as 1.
Address H'FF4C
Bit : 7 6 5 4 3 2 1 0
NDR15 NDR14 NDR13 NDR12 — — — —
Initial value : 0 0 0 0 1 1 1 1
R/W : R/W R/W R/W R/W — — — —
Address H'FF4E
Bit : 7 6 5 4 3 2 1 0
— — — — NDR11 NDR10 NDR9 NDR8
Initial value : 1 1 1 1 0 0 0 0
R/W : — — — — R/W R/W R/W R/W
If pulse output groups 0 and 1 are triggered by different compare match event, the address of the upper 4 bits in NDRL
(group 1) is H'FF4D and the address of the lower 4 bits (group 0) is H'FF4F. Bits 3 to 0 of address H'FF4D and bits 7 to 4
of address H'FF4F are reserved bits that cannot be modified and are always read as 1.