Renesas ZTAT H8S/2357F, Hardware Manual

Page: 258 / 1047

Rev.6.00 Oct.28.2004 page 230 of 1016
REJ09B0138-0600H
7.5.12 Write Data Buffer Function
DMAC internal-to-external dual address transfers and single address transfers can be executed at high speed using the
write data buffer function, enabling system throughput to be improved.
When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data buffer function, dual address
transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers)
are executed in parallel. Internal accesses are independent of the bus master, and DMAC dead cycles are regarded as
internal accesses.
A low level can always be output from the
TEND
pin if the bus cycle in which a low level is to be output is an external
bus cycle. However, a low level is not output from the
TEND
pin if the bus cycle in which a low level is to be output
from the
TEND
pin is an internal bus cycle, and an external write cycle is executed in parallel with this cycle.
Figure 7-33 shows an example of burst mode transfer from on-chip RAM to external memory using the write data buffer
function.
ø
Internal address
Internal read signal
HWR
,
LWR
TEND
External address
DMA
read DMA
write DMA
read DMA
write DMA
read DMA
write DMA
read DMA
write DMA
dead
Figure 7-33 Example of Dual Address Transfer Using Write Data Buffer Function
Figure 7-34 shows an example of single address transfer using the write data buffer function. In this example, the CPU
program area is in on-chip memory.