Renesas ZTAT H8S/2357F, Hardware Manual

Page: 202 / 1047

Rev.6.00 Oct.28.2004 page 174 of 1016
REJ09B0138-0600H
7.2.4 DMA Control Register (DMACR)
Bit : 7 6 5 4 3 2 1 0
DMACR : DTSZ DTID5 RPE DTDIR DTF3 DTF2 DTF1 DTF0
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
DMACR is an 8-bit readable/writable register that controls the operation of each DMAC channel.
DMACR is initialized to H'00 by a reset, and in hardware standby mode.
Bit 7—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time.
Bit 7
DTSZ
Description
0 Byte-size transfer (Initial value)
1 Word-size transfer
Bit 6—Data Transfer Increment/Decrement (DTID): Selects incrementing or decrementing of MAR every data transfer
in sequential mode or repeat mode.
In idle mode, MAR is neither incremented nor decremented.
Bit 6
DTID
Description
0 MAR is incremented after a data transfer (Initial value)
•
When DTSZ = 0, MAR is incremented by 1 after a transfer
•
When DTSZ = 1, MAR is incremented by 2 after a transfer
1 MAR is decremented after a data transfer
•
When DTSZ = 0, MAR is decremented by 1 after a transfer
•
When DTSZ = 1, MAR is decremented by 2 after a transfer
Bit 5—Repeat Enable (RPE): Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle,
or repeat) in which transfer is to be performed.
Bit 5
RPE DMABCR
DTIE
Description
0 0 Transfer in sequential mode (no transfer end interrupt) (Initial value)
1 Transfer in sequential mode (with transfer end interrupt)
1 0 Transfer in repeat mode (no transfer end interrupt)
1 Transfer in idle mode (with transfer end interrupt)
For details of operation in sequential, idle, and repeat mode, see section 7.5.2, Sequential Mode, section 7.5.3, Idle Mode,
and section 7.5.4, Repeat Mode.