Renesas ZTAT H8S/2357F, Hardware Manual

Page: 152 / 1047

Rev.6.00 Oct.28.2004 page 124 of 1016
REJ09B0138-0600H
6.3.5 Chip Select Signals
The H8S/2357 Group can output chip select signals (
CS0
to
CS7
) to areas 0 to 7, the signal being driven low when the
corresponding external space area is accessed.
Figure 6-3 shows an example of
CSn
(n = 0 to 7) output timing.
Enabling or disabling of the
CSn
signal is performed by setting the data direction register (DDR) for the port
corresponding to the particular
CSn
pin.
In ROM-disabled expansion mode, the
CS0
pin is placed in the output state after a power-on reset. Pins
CS1
to
CS7
are
placed in the input state after a power-on reset, and so the corresponding DDR should be set to 1 when outputting signals
CS1
to
CS7
.
In the ROM-enabled expansion mode, pins
CS0
to
CS7
are all placed in the input state after a power-on reset, and so the
corresponding DDR bits should be set to 1 when outputting signals
CS0
to
CS7
.
For details, see section 9, I/O Ports.
When areas 2 to 5 are designated as DRAM space, outputs
CS2
to
CS5
are used as
RAS
signals.
Bus cycle
T
1
T
2
T
3
Area n external address Address bus
ø
CSn
Figure 6-3
CSn
Signal Output Timing (n = 0 to 7)