Renesas ZTAT H8S/2357F, Hardware Manual

Page: 249 / 1047

Rev.6.00 Oct.28.2004 page 221 of 1016
REJ09B0138-0600H
Full Address Mode (Block Transfer Mode): Figure 7-22 shows a transfer example in which
TEND
output is enabled
and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to
external 16-bit, 2-state access space.
DMA
read
ø
Address bus
RD
LWR
TEND
HWR
Bus release Block transfer Last block transfer
DMA
write
DMA
read
DMA
write
DMA
dead DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead
Bus
release Bus release
Figure 7-22 Example of Full Address Mode (Block Transfer Mode) Transfer
A one-block transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is
released, one or more bus cycles are inserted by the CPU or DTC.
In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is
inserted after the DMA write cycle.
One block is transmitted without interruption. NMI generation does not affect block transfer operation.