Renesas ZTAT H8S/2357F, Hardware Manual

Page: 257 / 1047

Rev.6.00 Oct.28.2004 page 229 of 1016
REJ09B0138-0600H
DREQ
Pin Low Level Activation Timing: Set the DTA bit for the channel for which the
DREQ
pin is selected to 1.
Figure 7-32 shows an example of
DREQ
pin low level activated single address mode transfer.
ø
DREQ
Bus release DMA single
Address bus
DMA control
Channel
[2]
DACK
Transfer source/
destination
Idle Idle Idle Single Single
[1] [3] [5] [4] [6] [7]
Acceptance resumes Acceptance resumes
Bus release DMA single
Bus
release
Transfer source/
destination
Request Request
Minimum of
2 cycles
Minimum of
2 cycles
Request clear
period
Request clear
period
[1]
[2] [5]
[3] [6]
[4] [7]
Acceptance after transfer enabling; the
DREQ
pin low level is sampled on the rising
edge of ø, and the request is held.
The request is cleared at the next bus break, and activation is started in the DMAC.
The DMAC cycle is started.
Acceptance is resumed after the single cycle is completed.
(As in [1], the
DREQ
pin low level is sampled on the rising edge of ø, and the request is held.)
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7-32 Example of
DREQ
Pin Low Level Activated Single Address Mode Transfer
DREQ
pin sampling is performed every cycle, with the rising edge of the next ø cycle after the end of the DMABCR write
cycle for setting the transfer enabled state as the starting point.
When the
DREQ
pin low level is sampled while acceptance by means of the
DREQ
pin is possible, the request is held in
the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the single cycle,
acceptance resumes,
DREQ
pin low level sampling is performed again, and this operation is repeated until the transfer
ends.