Renesas ZTAT H8S/2357F, Hardware Manual

Page: 251 / 1047

Rev.6.00 Oct.28.2004 page 223 of 1016
REJ09B0138-0600H
Figure 7-24 shows an example of
DREQ
pin falling edge activated block transfer mode transfer.
[1]
[2] [5]
[3] [6]
[4] [7]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Acceptance after transfer enabling; the
DREQ
pin low level is sampled on the rising edge of ø,
and the request is held.
The request is cleared at the next bus break, and activation is started in the DMAC.
Start of DMA cycle;
DREQ
pin high level sampling on the rising edge of ø starts.
When the
DREQ
pin high level has been sampled, acceptance is resumed after the dead cycle
is completed.
(As in [1], the
DREQ
pin low level is sampled on the rising edge of ø, and the request is held.)
DMA
read
ø
Address bus
DREQ
Idle Write
Bus release
DMA control
Channel
Write
Transfer
source
Request
Minimun of 2 cycles
[1] [3] [2] [4] [6] [5] [7]
Acceptance resumes
DMA
dead
1 block transfer
Idle Dead Dead
DMA
write
Bus
release
DMA
read
DMA
write
DMA
dead Bus
release
Transfer
source
Transfer
destination
Request clear period
Minimun of 2 cycles
Request
Acceptance resumes
1 block transfer
Request clear period
Read Read
Transfer
destination
Idle
Figure 7-24 Example of
DREQ
Pin Falling Edge Activated Block Transfer Mode Transfer
DREQ
pin sampling is performed every cycle, with the rising edge of the next ø cycle after the end of the DMABCR write
cycle for setting the transfer enabled state as the starting point.
When the
DREQ
pin low level is sampled while acceptance by means of the
DREQ
pin is possible, the request is held in
the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and
DREQ
pin high level sampling
for edge detection is started. If
DREQ
pin high level sampling has been completed by the time the DMA dead cycle ends,
acceptance resumes after the end of the dead cycle,
DREQ
pin low level sampling is performed again, and this operation is
repeated until the transfer ends.