Rev.6.00 Oct.28.2004 page 1013
of 1016
REJ09B0138-0600H
Appendix F
Timing of Transition to and Recovery from Hardware
Standby Mode
F.1
Timing of Transition to Hardware Standby Mode
(1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the
RES
signal low at least 10 system clock
cycles before the
STBY
signal goes low, as shown below.
RES
must remain low until
STBY
signal goes low (delay
from
STBY
low to
RES
high: 0 ns or more).
STBY
RES
t
2
≥
0 ns
t
1
≥
10 t
cyc
Figure F-1 Timing of Transition to Hardware Standby Mode
(2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do not need to be retained,
RES
does not have to be driven low as in (1).
F.2
Timing of Recovery from Hardware Standby Mode
Drive the
RES
signal low and the NMI signal high approximately 100 ns or more before
STBY
goes high to execute a
power-on reset.
STBY
RES
t
OSC
t
NMIRH
t
≥
100 ns
NMI
Figure F-2 Timing of Recovery from Hardware Standby Mode
Summary of Contents for ZTAT H8S/2357F
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