Rev.6.00 Oct.28.2004 page 103
of 1016
REJ09B0138-0600H
Section 6 Bus Controller
6.1
Overview
The H8S/2357 Group has a on-chip bus controller (BSC) that manages the external address space divided into eight areas.
The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling
multiple memories to be connected easily.
The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU,
DMA controller (DMAC), and data transfer controller (DTC).
6.1.1
Features
The features of the bus controller are listed below.
•
Manages external address space in area units
In advanced mode, manages the external space as 8 areas of 2-Mbytes
Bus specifications can be set independently for each area
DRAM/burst ROM interfaces can be set
•
Basic bus interface
Chip select (
CS0
to
CS7
) can be output for areas 0 to 7
8-bit access or 16-bit access can be selected for each area
2-state access or 3-state access can be selected for each area
Program wait states can be inserted for each area
•
DRAM interface
DRAM interface can be set for areas 2 to 5 (in advanced mode)
Row address/column address multiplexed output (8/9/10 bits)
Two byte access methods (2-CAS)
Burst operation (fast page mode)
T
P
cycle insertion to secure RAS precharging time
Choice of CAS-before-RAS refreshing or self-refreshing
•
Burst ROM interface
Burst ROM interface can be set for area 0
Choice of 1- or 2-state burst access
•
Idle cycle insertion
An idle cycle can be inserted in case of an external read cycle between different areas
An idle cycle can be inserted in case of an external write cycle immediately after an external read cycle
•
Write buffer functions
External write cycle and internal access can be executed in parallel
DMAC single-address mode and internal access can be executed in parallel
•
Bus arbitration function
Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC, and DTC
Summary of Contents for ZTAT H8S/2357F
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