Renesas ZTAT H8S/2357F, Hardware Manual

Page: 790 / 1047

Rev.6.00 Oct.28.2004 page 762 of 1016
REJ09B0138-0600H
Condition B Condition C
Item Symbol Min Max Min Max Unit Test Conditions
Write data delay time t
WDD
— 30 — 60 ns Figure 22-72 to
Figure 22-79
Write data setup time t
WDS
0.5
×
t
cyc
– 20
— 0.5
×
t
cyc
– 36
— ns
Write data hold time t
WDH
0.5
×
t
cyc
– 10
— 0.5
×
t
cyc
– 20
— ns
WR
setup time t
WCS
0.5
×
t
cyc
– 10
— 0.5
×
t
cyc
– 20
— ns
WR
hold time t
WCH
0.5
×
t
cyc
– 10
— 0.5
×
t
cyc
– 20
— ns
CAS
setup time t
CSR
0.5
×
t
cyc
– 10
— 0.5
×
t
cyc
– 20
— ns Figure 22-76
WAIT
setup time t
WTS
30 — 60 — ns Figure 22-74
WAIT
hold time t
WTH
5 — 10 — ns
BREQ
setup time t
BRQS
30 — 60 — ns Figure 22-80
BACK
delay time t
BACD
— 15 — 30 ns
Bus-floating time t
BZD
— 50 — 100 ns
BREQO
delay time t
BRQOD
— 30 — 60 ns Figure 22-81
(4) DMAC Timing
Table 22-39 lists the DMAC timing.
Table 22-39 DMAC Timing
Condition B: V
CC
= 5.0 V
±
10%, AV
CC
= 5.0 V
±
10%, V
ref
= 4.5 V to AV
CC
,
V
SS
= AV
SS
= 0 V, ø = 2 to 20 MHz, T
a
= –20 to +75
°
C (regular specifications),
T
a
= –40 to +85
°
C (wide-range specifications)
Condition C: V
CC
= 3.0 V to 5.5 V, AV
CC
= 3.0 V to 5.5 V, V
ref
= 3.0 V to AV
CC
, V
SS
= AV
SS
= 0V, ø = 2 to 13 MHz, T
a
= –20 to +75
°
C (regular specifications), T
a
= –40 to +85
°
C (wide-range specifications)
Condition B Condition C
Item Symbol Min Max Min Max Unit Test Conditions
DREQ
setup time t
DRQS
30 — 40 — ns Figure 22-85
DREQ
hold time t
DRQH
10 — 10 —
TEND
delay time t
TED
— 20 — 40 Figure 22-84
DACK
delay time 1 t
DACD1
— 20 — 40 ns Figure 22-82
DACK
delay time 2 t
DACD2
— 20 — 40 Figure 22-83