Renesas ZTAT H8S/2357F, Hardware Manual

Page: 158 / 1047

Rev.6.00 Oct.28.2004 page 130 of 1016
REJ09B0138-0600H
16-Bit 2-State Access Space: Figures 6-8 to 6-10 show bus timings for a 16-bit 2-state access space. When a 16-bit
access space is accessed, the upper half (D
15
to D
8
) of the data bus is used for the even address, and the lower half (D
7
to
D
0
) for the odd address.
Wait states cannot be inserted.
Bus cycle
T
1
T
2
Address bus
ø
CSn
AS
RD
D
15
to D
8
Valid
D
7
to D
0
Invalid
Read
HWR
LWR
D
15
to D
8
Valid
D
7
to D
0
High impedance
Write
High
Note: n = 0 to 7
Figure 6-8 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access)