Renesas ZTAT H8S/2357F, Hardware Manual

Page: 201 / 1047

Rev.6.00 Oct.28.2004 page 173 of 1016
REJ09B0138-0600H
7.2.3 Execute Transfer Count Register (ETCR)
ETCR is a 16-bit readable/writable register that specifies the number of transfers. The setting of this register is different
for sequential mode and idle mode on the one hand, and for repeat mode on the other.
(1) Sequential Mode and Idle Mode
Transfer Counter
Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETCR :
Initial value : * * * * * * * * * * * * * * * *
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
* : Undefined
In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter (with a count range of 1 to 65,536). ETCR
is decremented by 1 each time a transfer is performed, and when the count reaches H'0000, the DTE bit in DMABCR is
cleared, and transfer ends.
(2) Repeat Mode
Transfer Number Storage
Bit : 15 14 13 12 11 10 9 8
ETCRH :
Initial value : * * * * * * * *
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
Transfer Counter
Bit : 7 6 5 4 3 2 1 0
ETCRL :
Initial value : * * * * * * * *
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
* : Undefined
In repeat mode, ETCR functions as transfer counter ETCRL (with a count range of 1 to 256) and transfer number storage
register ETCRH. ETCRL is decremented by 1 each time a transfer is performed, and when the count reaches H'00,
ETCRL is loaded with the value in ETCRH. At this point, MAR is automatically restored to the value it had when the
count was started. The DTE bit in DMABCR is not cleared, and so transfers can be performed repeatedly until the DTE bit
is cleared by the user.
ETCR is not initialized by a reset or in standby mode.