Renesas ZTAT H8S/2357F, Hardware Manual

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Rev.6.00 Oct.28.2004 page 294 of 1016
REJ09B0138-0600H
9.6 Port 5
9.6.1 Overview
Port 5 is a 4-bit I/O port. Port 5 pins also function as SCI I/O pins (TxD2, RxD2, and SCK2) and the A/D converter input
pin (
ADTRG
). Port 5 pin functions are the same in all operating modes. Figure 9-5 shows the port 5 pin configuration.
P5
3
(I/O)/
ADTRG
(input)
P5
2
(I/O)/SCK2 (I/O)
P5
1
(I/O)/RxD2 (input)
P5
0
(I/O)/TxD2 (output)
Port 5 pins
Port 5
Figure 9-5 Port 5 Pin Functions
9.6.2 Register Configuration
Table 9-9 shows the port 5 register configuration.
Table 9-9 Port 5 Registers
Name Abbreviation R/W Initial Value *
2
Address *
1
Port 5 data direction register P5DDR W H'0 H'FEB4
Port 5 data register P5DR R/W H'0 H'FF64
Port 5 register PORT5 R Undefined H'FF54
Notes: 1. Lower 16 bits of the address.
2. Value of bits 3 to 0.
Port 5 Data Direction Register (P5DDR)
Bit : 7 6 5 4 3 2 1 0
— — — — P53DDR P52DDR P51DDR P50DDR
Initial value :
Undefined Undefined Undefined Undefined
0 0 0 0
R/W : — — — — W W W W
P5DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 5. Bits 7 to 4
are reserved. P5DDR cannot be read; if it is, an undefined value will be read.
Setting a P5DDR bit to 1 makes the corresponding port 5 pin an output pin, while clearing the bit to 0 makes the pin an
input pin.
P5DDR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a
manual reset*, and in software standby mode. As the SCI is initialized, the pin states are determined by the P5DDR and
P5DR specifications.