Rev.6.00 Oct.28.2004 page 536
of 1016
REJ09B0138-0600H
M =
(0.5 –
1
2N
) – (L – 0.5) F –
D – 0.5
N
(1 + F
) ×
100%
Where M: Reception margin (%)
N: Ratio of bit rate to clock (N = 372)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
Assuming values of F = 0 and D = 0.5 in the above formula, the reception margin formula is as follows.
When D = 0.5 and F = 0,
M = (0.5 – 1/2
×
372)
×
100%
= 49.866%
Retransfer Operations: Retransfer operations are performed by the SCI in receive mode and transmit mode as described
below.
•
Retransfer operation when SCI is in receive mode
Figure 15-11 illustrates the retransfer operation when the SCI is in receive mode.
[1] If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit
in SCR is enabled at this time, an ERI interrupt request is generated. The PER bit in SSR should be kept cleared to 0
until the next parity bit is sampled.
[2] The RDRF bit in SSR is not set for a frame in which an error has occurred.
[3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1.
[4] If no error is found when the received parity bit is checked, the receive operation is judged to have been completed
normally, and the RDRF flag in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI
interrupt request is generated.
If DMAC or DTC data transfer by an RXI source is enabled, the contents of RDR can be read automatically. When the
RDR data is read by the DMAC or DTC, the RDRF flag is automatically cleared to 0.
[5] When a normal frame is received, the pin retains the high-impedance state at the timing for error signal transmission.
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(DE)
Ds D0 D1 D2 D3 D4
Ds
Transfer
frame n+1
Retransferred frame
nth transfer frame
RDRF
[1]
PER
[2]
[3]
[4]
Figure 15-11 Retransfer Operation in SCI Receive Mode
•
Retransfer operation when SCI is in transmit mode
Figure 15-12 illustrates the retransfer operation when the SCI is in transmit mode.
[6] If an error signal is sent back from the receiving end after transmission of one frame is completed, the ERS bit in SSR
is set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The ERS bit in SSR
should be kept cleared to 0 until the next parity bit is sampled.
Summary of Contents for ZTAT H8S/2357F
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