Renesas ZTAT H8S/2357F, Hardware Manual

Page: 483 / 1047

Rev.6.00 Oct.28.2004 page 455 of 1016
REJ09B0138-0600H
13.1.4 Register Configuration
The WDT has three registers, as summarized in table 13-2. These registers control clock selection, WDT mode switching,
and the reset signal.
Table 13-2 WDT Registers
Address
*
1
Name Abbreviation R/W Initial Value Write
*
2
Read
Timer control/status register TCSR R/(W)
*
3
H'18 H'FFBC H'FFBC
Timer counter TCNT R/W H'00 H'FFBC H'FFBD
Reset control/status register RSTCSR R/(W)
*
3
H'1F H'FFBE H'FFBF
Notes: 1. Lower 16 bits of the address.
2. For details of write operations, see section 13.2.4, Notes on Register Access.
3. Only a write of 0 is permitted to bit 7, to clear the flag.