Renesas ZTAT H8S/2357F, Hardware Manual

Page: 777 / 1047

Rev.6.00 Oct.28.2004 page 749 of 1016
REJ09B0138-0600H
(5) Timing of On-Chip Supporting Modules
Table 22-30 lists the timing of on-chip supporting modules.
Table 22-30 Timing of On-Chip Supporting Modules
Condition A: V
CC
= 2.7 V to 5.5 V, AV
CC
= 2.7 V to 5.5 V, V
ref
= 2.7 V to AV
CC
,
V
SS
= AV
SS
= 0 V, ø = 2 to 10 MHz, T
a
= –20 to +75
°
C (regular specifications),
T
a
= –40 to +85
°
C (wide-range specifications)
Condition B: V
CC
= 5.0 V
±
10%, AV
CC
= 5.0 V
±
10%, V
ref
= 4.5 V to AV
CC
,
V
SS
= AV
SS
= 0 V, ø = 2 to 20 MHz, T
a
= –20 to +75
°
C (regular specifications),
T
a
= –40 to +85
°
C (wide-range specifications)
Condition C: V
CC
= 3.0 to 5.5 V, AV
CC
= 3.0 to 5.5 V, V
ref
= 3.0 V to AV
CC
,
V
SS
= AV
SS
= 0 V, ø = 2 to 13 MHz, T
a
= –20 to +75
°
C (regular specifications),
T
a
= –40 to +85
°
C (wide-range specifications)
Condition A Condition B Condition C
Test
Item Symbol Min Max Min Max Min Max Unit Conditions
PORT Output data delay time t
PWD
— 100 — 50 — 75 ns Figure 22-86
Input data setup time t
PRS
50 — 30 — 50 —
Input data hold time t
PRH
50 — 30 — 50 —
PPG Pulse output delay time t
POD
— 100 — 50 — 75 ns Figure 22-87
TPU Timer output delay time t
TOCD
— 100 — 50 — 75 ns Figure 22-88
Timer input setup time t
TICS
50 — 30 — 50 —
Timer clock input setup
time t
TCKS
50 — 30 — 50 — ns Figure 22-89
Timer clock
pulse width Single
edge t
TCKWH
1.5 — 1.5 — 1.5 — t
cyc
Both
edges t
TCKWL
2.5 — 2.5 — 2.5 —
TMR Timer output delay time t
TMOD
— 100 — 50 — 75 ns Figure 22-90
Timer reset input setup
time t
TMRS
50 — 30 — 50 — ns Figure 22-92
Timer clock input setup
time t
TMCS
50 — 30 — 50 — ns Figure 22-91
Timer clock
pulse width Single
edge t
TMCWH
1.5 — 1.5 — 1.5 — t
cyc
Both
edges t
TMCWL
2.5 — 2.5 — 2.5 —
WDT Overflow output delay
time
t
WOVD
— 100 — 50 — 75 ns Figure 22-93
SCI Input clock
cycle Asynchro-
nous t
Scyc
4 — 4 — 4 — t
cyc
Figure 22-94
Synchro-
nous 6 — 6 — 6 —
Input clock pulse width t
SCKW
0.4 0.6 0.4 0.6 0.4 0.6 t
Scyc
Input clock rise time t
SCKr
— 1.5 — 1.5 — 1.5 t
cyc
Input clock fall time t
SCKf
— 1.5 — 1.5 — 1.5