Renesas ZTAT H8S/2357F, Hardware Manual

Page: 220 / 1047

Rev.6.00 Oct.28.2004 page 192 of 1016
REJ09B0138-0600H
7.4.2 DMA Terminal Control Register (DMATCR)
Bit : 7 6 5 4 3 2 1 0
DMATCR : — — TEE1 TEE0 — — — —
Initial value : 0 0 0 0 0 0 0 0
R/W : — — R/W R/W — — — —
DMATCR is an 8-bit readable/writable register that controls enabling or disabling of DMAC transfer end pin output. A
port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit.
DMATCR is initialized to H'00 by a reset, and in standby mode.
Bits 7 and 6—Reserved: These bits cannot be modified and are always read as 0.
Bit 5—Transfer End Enable 1 (TEE1): Enables or disables transfer end pin 1 (
TEND1
) output.
Bit 5
TEE1
Description
0
TEND1
pin output disabled (Initial value)
1
TEND1
pin output enabled
Bit 4—Transfer End Enable 0 (TEE0): Enables or disables transfer end pin 0 (
TEND0
) output.
Bit 4
TEE0
Description
0
TEND0
pin output disabled (Initial value)
1
TEND0
pin output enabled
The
TEND
pins are assigned only to channel B in short address mode.
The transfer end signal indicates the transfer cycle in which the transfer counter reached 0, regardless of the transfer
source. An exception is block transfer mode, in which the transfer end signal indicates the transfer cycle in which the
block counter reached 0.
Bits 3 to 0—Reserved: These bits cannot be modified and are always read as 0.