Renesas ZTAT H8S/2357F Hardware Manual Download Page 119 | Manualshive

Page: 119 / 1047

background image

Rev.6.00 Oct.28.2004 page 91

of 1016

REJ09B0138-0600H

Origin of

Vector
Address

*

Interrupt Source

Interrupt
Source

Vector
Number

Advanced
Mode

IPR

Priority

ERI0 (receive error 0)

RXI0 (reception data full 0)

TXI0 (transmit data empty 0)

TEI0 (transmission end 0)

SCI
channel 0

80

81

82

83

H'0140

H'0144

H'0148

H'014C

IPRJ2 to 0

High

ERI1 (receive error 1)

RXI1 (reception data full 1)

TXI1 (transmit data empty 1)

TEI1 (transmission end 1)

SCI
channel 1

84

85

86

87

H'0150

H'0154

H'0158

H'015C

IPRK6 to 4

ERI2 (receive error 2)

RXI2 (reception data full 2)

TXI2 (transmit data empty 2)

TEI2 (transmission end 2)

SCI
channel 2

88

89

90

91

H'0160

H'0164

H'0168

H'016C

IPRK2 to 0

Low

Note:

*

Lower 16 bits of the start address.

5.4

Interrupt Operation

5.4.1

Interrupt Control Modes and Interrupt Operation

Interrupt operations in the H8S/2357 Group differ depending on the interrupt control mode.

NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ
interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to
0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the
interrupt controller.

Table 5-5 shows the interrupt control modes.

The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0
bits in SYSCR, the priorities set in IPR, and the masking state indicated by the I and UI bits in the CPU’s CCR, and bits I2
to I0 in EXR.

Table 5-5

Interrupt Control Modes

Interrupt

SYSCR

Priority Setting

Interrupt

Control Mode INTM1 INTM0 Registers

Mask Bits Description

0

0

0

—

I

Interrupt mask control is
performed by the I bit.

—

1

—

—

Setting prohibited

2

1

0

IPR

I2 to I0

8-level interrupt mask control
is performed by bits I2 to I0.
8 priority levels can be set with
IPR.

—

1

—

—

Setting prohibited

«
...
117
118
119
120
121
...
»

Summary of Contents for ZTAT H8S/2357F

Page 1: ...357F ZTATTM H8S 2398F ZTATTM 16 Rev 6 00 Revision date Oct 28 2004 REJ09B0138 0600H www renesas com The revision list can be viewed directly by clicking the title page The revision list summarizes the...

Page 2: ...fore making a final decision on the applicability of the information and products Renesas Technology Corp assumes no responsibility for any damage liability or other loss resulting from the informatio...

Page 3: ...e When power is first supplied the product s state is undefined The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin...

Page 4: ......

Page 5: ...e are expected to understand the fundamentals of electrical circuits logical circuits and microcomputers Objective This manual was written to explain the hardware functions and electrical characterist...

Page 6: ...H8 300 Series C C Compiler Assembler Optimized Linkage Editor User s Manual REJ10B0058 H8S H8 300 Series Simulator Debugger for Windows User s Manual ADE 702 037 H8S H8 300 Series High performance Em...

Page 7: ...ption amended In modes 6 and 7 the on chip ROM In this case clearing the EAE bit in BCRL enables the 128 kbyte 256 kbytes area comprising address H 000000 to H 01FFFF H 03FFFF to be used 6 6 1 When DD...

Page 8: ...B MOS Pull Up Control Register PBPCR ON Chip ROM Version Only Bit 7 6 5 4 3 2 1 0 PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W...

Page 9: ...383 Figure 10 23 amended Before TCLKA After TCLKC Before TCLKB After TCLKD 10 7 Usage Note Figure 10 57 Contention between TCNT Write and Overflow 409 Figure 10 57 amended TCFV flag Prohibited 11 3 1...

Page 10: ...ear SWE bit in FLMCR1 m 1 128 byte data verification completed m 0 6 n 6 n Increment address Programming failure OK Clear SWE bit in FLMCR1 n N Write 128 byte data in RAM reprogram data area consecuti...

Page 11: ...ion Cycles 827 Table A 6 amended Instruction JMP aa 8 Advanced R W NEXT R W M aa 8 R W aa 8 Internal operation R W EA 1 state JSR ERn Advanced R W NEXT R W EA W W M stack H W W stack L JSR aa 24 Advan...

Page 12: ...G 2 amended H8S 2398 Masked ROM HD6432398 HD6432398TE 1 120 pin TQFP TFP 120 HD6432398F 1 128 pin QFP FP 128B F ZTAT HD64F2398 HD64F2398TE 1 120 pin TQFP TFP 120 HD64F2398F 1 128 pin QFP FP 128B HD64...

Page 13: ...tial Register Values 29 2 5 Data Formats 30 2 5 1 General Register Data Formats 30 2 5 2 Memory Data Formats 32 2 6 Instruction Set 33 2 6 1 Overview 33 2 6 2 Instructions and Addressing Modes 34 2 6...

Page 14: ...3 3 9 Mode 10 H8S 2357 F ZTAT Only 61 3 3 10 Mode 11 H8S 2357 F ZTAT Only 61 3 3 11 Modes 12 and 13 H8S 2357 F ZTAT Only 61 3 3 12 Mode 14 H8S 2357 F ZTAT Only 61 3 3 13 Mode 15 H8S 2357 F ZTAT Only 6...

Page 15: ...EPMOV Instruction 100 5 6 DTC and DMAC Activation by Interrupt 100 5 6 1 Overview 100 5 6 2 Block Diagram 101 5 6 3 Operation 101 5 6 4 Note on Use 102 Section 6 Bus Controller 103 6 1 Overview 103 6...

Page 16: ...Cycle 157 6 9 Write Data Buffer Function 158 6 10 Bus Release 159 6 10 1 Overview 159 6 10 2 Operation 159 6 10 3 Pin States in External Bus Released State 160 6 10 4 Transition Timing 161 6 10 5 Usag...

Page 17: ...0 7 5 13 DMAC Multi Channel Operation 231 7 5 14 Relation between External Bus Requests Refresh Cycles the DTC and the DMAC 232 7 5 15 NMI Interrupts and DMAC 233 7 5 16 Forced Termination of DMAC Ope...

Page 18: ...4 293 9 5 1 Overview 293 9 5 2 Register Configuration 293 9 5 3 Pin Functions 293 9 6 Port 5 294 9 6 1 Overview 294 9 6 2 Register Configuration 294 9 6 3 Pin Functions 296 9 7 Port 6 297 9 7 1 Overv...

Page 19: ...Descriptions 345 10 2 1 Timer Control Register TCR 345 10 2 2 Timer Mode Register TMDR 349 10 2 3 Timer I O Control Register TIOR 351 10 2 4 Timer Interrupt Enable Register TIER 361 10 2 5 Timer Stat...

Page 20: ...ted Pulse Output 429 11 3 6 Pulse Output Triggered by Input Capture 430 11 4 Usage Notes 431 Section 12 8 Bit Timers 433 12 1 Overview 433 12 1 1 Features 433 12 1 2 Block Diagram 434 12 1 3 Pin Confi...

Page 21: ...Interrupts 462 13 5 Usage Notes 463 13 5 1 Contention between Timer Counter TCNT Write and Increment 463 13 5 2 Changing Value of CKS2 to CKS0 463 13 5 3 Switching between Watchdog Timer Mode and Inte...

Page 22: ...sage Notes 535 Section 16 A D Converter 539 16 1 Overview 539 16 1 1 Features 539 16 1 2 Block Diagram 540 16 1 3 Pin Configuration 540 16 1 4 Register Configuration 541 16 2 Register Descriptions 542...

Page 23: ...5 1 Overview 569 19 5 2 Programming and Verification 570 19 5 3 Programming Precautions 572 19 5 4 Reliability of Programmed Data 573 19 6 Overview of Flash Memory H8S 2357 F ZTAT 574 19 6 1 Features...

Page 24: ...lation in RAM 624 19 15 6 Differences between Boot Mode and User Program Mode 625 19 15 7 Block Configuration 625 19 15 8 Pin Configuration 626 19 15 9 Register Configuration 626 19 16 Register Descri...

Page 25: ...65 Section 21 Power Down Modes 667 21 1 Overview 667 21 1 1 Register Configuration 668 21 2 Register Descriptions 669 21 2 1 Standby Control Register SBYCR 669 21 2 2 System Clock Control Register SCK...

Page 26: ...cteristics 753 22 6 5 D A Convervion Characteristics 754 22 7 Electrical Characteristics of H8S 2357 F ZTAT Version 755 22 7 1 Absolute Maximum Ratings 755 22 7 2 DC Characteristics 755 22 7 3 AC Char...

Page 27: ...wer On 1011 E 1 When Pins Settle from an Indeterminate State at Power On 1011 E 2 When Pins Settle from the High Impedance State at Power On 1012 Appendix F Timing of Transition to and Recovery from H...

Page 28: ...Rev 6 00 Oct 28 2004 page xxiv of xxiv REJ09B0138 0600H...

Page 29: ...tating migration from the H8 300 H8 300L or H8 300H Series On chip peripheral functions required for system configuration include DMA controller DMAC and data transfer controller DTC bus masters ROM a...

Page 30: ...d into 8 areas with bus specifications settable independently for each area Chip select output possible for each area Choice of 8 bit or 16 bit access space for each area 2 state or 3 state access spa...

Page 31: ...Watchdog timer Watchdog timer or interval timer selectable Serial communication interface SCI 3 channels Asynchronous mode or synchronous mode selectable Multiprocessor communication function Smart c...

Page 32: ...andby mode Hardware standby mode Operating modes Eight MCU operating modes H8S 2357 F ZTAT CPU External Data Bus Mode Operating Mode Description On Chip ROM Initial Value Maximum Value 0 1 2 3 4 Advan...

Page 33: ...128 pin plastic QFP FP 128B Product 5 V version 3 3 V version 3 V version lineup Operating Supply Voltage 5 V 10 3 0 to 5 5 V 2 7 to 5 5 V Operating Frequency 2 to 20 MHz 10 to 20 MHz 2 to 13 MHz 2 to...

Page 34: ...TIOCA0 DACK0 P1 1 PO9 TIOCB0 DACK1 P1 2 PO10 TIOCC0 TCLKA P1 3 PO11 TIOCD0 TCLKB P1 4 PO12 TIOCA1 P1 5 PO13 TIOCB1 TCLKC P1 6 PO14 TIOCA2 P1 7 PO15 TIOCB2 TCLKD P67 CS7 IRQ3 P66 CS6 IRQ2 P65 IRQ1 P64...

Page 35: ...2 7 PO7 TIOCB5 TMO1 P6 3 TEND1 P6 2 DREQ1 P6 1 TEND0 CS5 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43...

Page 36: ...2 DREQ1 P6 1 TEND0 CS5 V SS V SS P6 0 DREQ0 CS4 V SS 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55...

Page 37: ...D1 P6 2 DREQ1 P6 1 TEND0 CS5 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34...

Page 38: ...P2 5 PO5 TIOCB4 TMCI1 P2 6 PO6 TIOCA5 TMO0 P2 7 PO7 TIOCB5 TMO1 P6 3 TEND1 P6 2 DREQ1 P6 1 TEND0 CS5 V SS V SS P6 0 DREQ0 CS4 V SS 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81...

Page 39: ...12 16 A9 A9 PB1 A9 PB1 OE NC A9 3 13 17 A10 A10 PB2 A10 PB2 A10 A10 14 18 A11 A11 PB3 A11 PB3 A11 A11 15 19 VSS VSS VSS VSS VSS VSS 16 20 A12 A12 PB4 A12 PB4 A12 A12 17 21 A13 A13 PB5 A13 PB5 A13 A13...

Page 40: ...S VSS 48 54 D12 D12 D12 PD4 D4 I O4 49 55 D13 D13 D13 PD5 D5 I O5 50 56 D14 D14 D14 PD6 D6 I O6 51 57 D15 D15 D15 PD7 D7 I O7 52 58 VCC VCC VCC VCC VCC VCC 53 59 P30 TxD0 P30 TxD0 P30 TxD0 P30 TxD0 NC...

Page 41: ...CL 2 73 81 RES RES RES RES VPP RES 74 82 NMI NMI NMI NMI A9 A9 VCC 3 75 83 STBY STBY STBY STBY VSS VCC 76 84 VCC VCC VCC VCC VCC VCC 77 85 XTAL XTAL XTAL XTAL NC XTAL 78 86 EXTAL EXTAL EXTAL EXTAL NC...

Page 42: ...CD0 TCLKB NC NC 110 120 P12 PO10 TIOCC0 TCLKA P12 PO10 TIOCC0 TCLKA P12 PO10 TIOCC0 TCLKA P12 PO10 TIOCC0 TCLKA NC NC 111 121 P11 PO9 TIOCB0 DACK1 P11 PO9 TIOCB0 DACK1 P11 PO9 TIOCB0 DACK1 P11 PO9 TIO...

Page 43: ...pins should be connected to the system power supply 0 V Internal voltage step down drop pin VCL 1 72 80 INPUT Connects an external capacitor between this pin and the ground pin 0 V This pin should ne...

Page 44: ...level At power on the NMI pin input level should be set high STBY 75 83 Input Standby When this pin is driven low a transition is made to hardware standby mode BREQ 88 96 Input Bus request Used by an...

Page 45: ...gnal that writes to external space and indicates that the upper half D15 to D8 of the data bus is enabled The 2CAS type DRAM write enable signal LWR 85 93 Output Low write A strobe signal that writes...

Page 46: ...4 I O Input capture output compare match A4 and B4 The TGR4A and TGR4B input capture input or output compare output or PWM output pins TIOCA5 TIOCB5 65 64 73 72 I O Input capture output compare match...

Page 47: ...this pin should be connected to the system power supply 5 V I O ports P17 to P10 112 to 105 122 to 115 I O Port 1 An 8 bit I O port Input or output can be designated for each bit by means of the port...

Page 48: ...each bit by means of the port D data direction register PDDDR PE7 to PE0 42 to 39 37 to 34 48 to 45 43 to 40 I O Port E An 8 bit I O port Input or output can be designated for each bit by means of the...

Page 49: ...ructions 8 16 32 bit arithmetic and logic instructions Multiply and divide instructions Powerful bit manipulation instructions Eight addressing modes Register direct Rn Register indirect ERn Register...

Page 50: ...5 21 There are also differences in the address space CCR and EXR functions power down state etc depending on the product 2 1 3 Differences from H8 300 CPU In comparison to the H8 300 CPU the H8S 2000...

Page 51: ...ing Modes The H8S 2357 Group CPU has advanced operating mode Advanced mode supports a maximum 16 Mbyte total address space architecturally a maximum 16 Mbyte program area and a maximum of 4 Gbytes for...

Page 52: ...or system use Reserved Exception vector 1 Reserved Manual reset exception vector H 00000010 Note Manual reset is only supported in the H8S 2357 ZTAT H 00000008 H 00000007 Figure 2 1 Exception Vector T...

Page 53: ...ushed onto the stack in exception handling they are stored as shown in figure 2 2 When EXR is invalid it is not pushed onto the stack For details see section 4 Exception Handling a Subroutine Branch b...

Page 54: ...hows a memory map of the H8S 2000 CPU The H8S 2000 CPU provides linear access to a maximum 16 Mbyte architecturally 4 Gbyte address space in advanced mode Advanced Mode H 00000000 H FFFFFFFF H 00FFFFF...

Page 55: ...as an interrupt mask ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 SP I UI H U N Z V C CCR 7 6 5 4 3 2 1 0 Half carry flag User bit Negative flag Zero flag Overflow flag Carry flag H U N Z V C Figure 2 4 CPU Regist...

Page 56: ...exception handling and subroutine calls Figure 2 6 shows the stack Free area Stack area SP ER7 Figure 2 6 Stack 2 4 3 Control Registers The control registers are the 24 bit program counter PC 8 bit ex...

Page 57: ...SUB L CMP L or NEG L instruction is executed the H flag is set to 1 if there is a carry or borrow at bit 27 and cleared to 0 otherwise Bit 4 User Bit U Can be written and read by software using the L...

Page 58: ...ructions treat byte data as two digits of 4 bit BCD data 2 5 1 General Register Data Formats Figure 2 7 shows the data formats in general registers 7 6 5 4 3 2 1 0 Don t care 7 0 Don t care 7 6 5 4 3...

Page 59: ...6 MSB 31 En Rn General register ER General register E General register R General register RH General register RL Most significant bit Least significant bit Legend ERn En Rn RnH RnL MSB LSB 0 MSB LSB 1...

Page 60: ...error occurs but the least significant bit of the address is regarded as 0 so the access starts at the preceding address This also applies to instruction fetches 7 6 5 4 3 2 1 0 7 0 MSB LSB MSB LSB MS...

Page 61: ...ations AND OR XOR NOT BWL 4 Shift SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR BWL 8 Bit manipulation BSET BCLR BNOT BTST BLD BILD BST BIST BAND BIAND BOR BIOR BXOR BIXOR B 14 Branch Bcc 2 JMP BSR JSR RT...

Page 62: ...BWL BWL SUB WL BWL ADDX SUBX B B ADDS SUBS L INC DEC BWL DAA DAS B NEG BWL EXTU EXTS WL TAS 2 B Notes 1 Cannot be used in the H8S 2357 Group 2 Only register ER0 ER1 ER4 or ER5 should be used when usin...

Page 63: ...Ad Destination operand EAs Source operand EXR Extended control register CCR Condition code register N N negative flag in CCR Z Z zero flag in CCR V V overflow flag in CCR C C carry flag in CCR PC Prog...

Page 64: ...ubtraction on data in two general registers or on immediate data and data in a general register Immediate byte data cannot be subtracted from byte data in a general register Use the SUBX or ADD instru...

Page 65: ...bits of a 16 bit register to word size or the lower 16 bits of a 32 bit register to longword size by extending the sign bit TAS B ERd 0 1 bit 7 of ERd 2 Tests memory contents and sets the most signifi...

Page 66: ...result in the carry flag C bit No of EAd C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag The bit number is spe...

Page 67: ...BVC Overflow clear V 0 BVS Overflow set V 1 BPL Plus N 0 BMI Minus N 1 BGE Greater or equal N V 0 BLT Less than N V 1 BGT Greater than Z N V 0 BLE Less or equal Z N V 1 JMP Branches unconditionally to...

Page 68: ...increments the program counter Block data transfer instruction EEPMOV B EEPMOV W if R4L 0 then Repeat ER5 ER6 R4L 1 R4L Until R4L 0 else next if R4 0 then Repeat ER5 ER6 R4 1 R4 Until R4 0 else next...

Page 69: ...e instructions have two operation fields 2 Register Field Specifies a general register Address registers are specified by 3 bits data registers by 3 bits or 4 bits Some instructions have two register...

Page 70: ...crement ERn The register field of the instruction code specifies an address register ERn which contains the address of a memory operand After the operand is accessed 1 2 or 4 is added to the address r...

Page 71: ...upper 8 bits are all assumed to be 0 H 00 The PC value to which the displacement is added is the address of the first byte of the next instruction so the possible branching range is 126 to 128 bytes...

Page 72: ...ddress Calculation Effective Address EA 1 Register direct Rn op rm rn Operand is general register contents Register indirect ERn 2 Register indirect with displacement d 16 ERn or d 32 ERn 3 Register i...

Page 73: ...te xx 8 xx 16 xx 32 31 0 8 7 Operand is immediate data No Addressing Mode and Instruction Format Effective Address Calculation Effective Address EA aa 24 31 0 16 15 31 0 24 23 31 0 op abs op abs abs o...

Page 74: ...ve d 8 PC d 16 PC 8 Memory indirect aa 8 Advanced mode No Addressing Mode and Instruction Format Effective Address Calculation Effective Address EA 23 23 0 31 8 7 0 disp abs H 000000 31 0 24 23 31 0 2...

Page 75: ...and are stopped Exception handling state A transient state in which the CPU changes the normal processing flow in response to a reset interrupt or trap instruction Program execution state The CPU exe...

Page 76: ...he CPU enters the power on reset state when the NMI pin is high or the manual reset state when the NMI pin is low All interrupts are masked in the reset state Reset exception handling starts when the...

Page 77: ...s The CPU enters the power on reset state when the NMI pin is high or the manual reset state when the NMI pin is low When reset exception handling starts the CPU fetches a start address vector from th...

Page 78: ...here are three modes in which the CPU stops operating sleep mode software standby mode and hardware standby mode There are also two other power down modes medium speed mode and module stop mode In med...

Page 79: ...ng edge of to the next is referred to as a state The memory cycle or bus cycle consists of one two or three states Different methods are used to access on chip memory on chip supporting modules and th...

Page 80: ...odules are accessed in two states The data bus is either 8 bits or 16 bits wide depending on the particular internal I O register being accessed Figure 2 16 shows the access timing for the on chip sup...

Page 81: ...8 bit or 16 bit data bus width in a two state or three state bus cycle In three state access wait states can be inserted For further details refer to section 6 Bus Controller 2 10 Usage Note 2 10 1 T...

Page 82: ...Rev 6 00 Oct 28 2004 page 54 of 1016 REJ09B0138 0600H...

Page 83: ...d mode Enabled 8 bits 16 bits 7 1 Single chip mode 8 1 0 0 0 9 1 10 1 0 Advanced Boot mode Enabled 8 bits 16 bits 11 1 12 1 0 0 13 1 14 1 0 Advanced User program mode Enabled 8 bits 16 bits 15 1 The C...

Page 84: ...its 16 bits 7 1 Single chip mode Notes 1 In the H8S 2398 F ZTAT modes 2 and 3 indicate boot mode For details on boot mode of the H8S 2398 F ZTAT version refer to table 19 35 in section 19 17 On Board...

Page 85: ...Control Register MDCR Bit 7 6 5 4 3 2 1 0 MDS2 MDS1 MDS0 Initial value 1 0 0 0 0 R W R R R Note Determined by pins MD2 to MD0 MDCR is an 8 bit read only register that indicates the current operating...

Page 86: ...the rising edge of NMI input Bit 2 Reserved This bit cannot be modified and is always read as 0 This bit is reserved in the H8S 2390 H8S 2392 H8S 2394 and H8S 2398 Only 0 should be written to this bi...

Page 87: ...control registers FLMCR1 FLMCR2 EBR1 and EBR2 For details see section 19 ROM Bit 3 FLSHE Description 0 Flash control registers are not selected for addresses H FFFFC8 to H FFFFCB Initial value 1 Flash...

Page 88: ...ip ROM Disabled Expansion Mode The CPU can access a 16 Mbyte address space in advanced mode The on chip ROM is disabled Ports A B and C function as an address bus ports D and E function as a data bus...

Page 89: ...mode For details see section 19 ROM MCU operation is the same as in mode 6 3 3 10 Mode 11 H8S 2357 F ZTAT Only This is a flash memory boot mode For details see section 19 ROM MCU operation is the sam...

Page 90: ...Port D D P D D D P D P D P Port E P 1 D P P D 1 P 1 D P 1 D P P 1 D P P 1 D P Port F PF7 P C 1 P C 1 P C 1 P C 1 P C 1 P 1 C P C 1 P 1 C P C 1 P 1 C PF6 to PF3 C P C C C P C P C P PF2 to PF0 P 1 C P 1...

Page 91: ...re provided in the H8S 2352 Internal I O registers On chip ROM On chip ROM reserved area 2 External address space External address space Internal I O registers External address space On chip RAM 3 On...

Page 92: ...RAME bit to 0 in SYSCR 4 Modes 10 and 11 are provided in the F ZTAT version only On chip ROM External address space On chip RAM 3 On chip RAM 3 On chip ROM reserved area 2 Internal I O registers Exte...

Page 93: ...lear the RAME bit to 0 in SYSCR 4 Modes 14 and 15 are provided in the F ZTAT version only On chip ROM External address space On chip RAM 3 On chip RAM 3 On chip ROM reserved area 2 Internal I O regist...

Page 94: ...ace is inhibited The space can be made available for use as an external address space by clearing the RAME bit of the SYSCR to 0 2 External addresses can be accessed by clearing the RAME bit in SYSCR...

Page 95: ...ternal address space On chip RAM Note External addresses can be accessed by clearing the RAME bit in SYSCR to 0 Internal I O registers External address space Internal I O registers External address sp...

Page 96: ...ternal address space On chip RAM Note External addresses can be accessed by clearing the RAME bit in SYSCR to 0 Internal I O registers External address space Internal I O registers External address sp...

Page 97: ...o 0 4 Access to the reserved area is inhibited 5 Modes 2 and 3 are provided in the F ZTAT version only On chip ROM On chip ROM reserved area 2 4 External address space On chip RAM 3 On chip RAM 3 Inte...

Page 98: ...reserved area is inhibited Internal I O registers On chip ROM On chip ROM reserved area 2 4 External address space External address space Internal I O registers External address space On chip RAM 3 On...

Page 99: ...y after a low to high transition at the RES pin or when the watchdog timer overflows The CPU enters the power on reset state when the NMI pin is high or the manual reset 4 state when the NMI pin is lo...

Page 100: ...es are assigned to different exception sources Table 4 2 lists the exception sources and their vector addresses Exception sources Note Manual reset is only supported in the H8S 2357 ZTAT Reset Trace I...

Page 101: ...H 0023 9 H 0024 to H 0027 10 H 0028 to H 002B 11 H 002C to H 002F Reserved for system use 12 H 0030 to H 0033 13 H 0034 to H 0037 14 H 0038 to H 003B 15 H 003C to H 003F External interrupt IRQ0 16 H...

Page 102: ...tchdog Timer Note Manual reset is only supported in the H8S 2357 ZTAT 4 2 2 Reset Types A reset can be of either of two types a power on reset or a manual reset Reset types are shown in table 4 3 A po...

Page 103: ...ters of the on chip supporting modules are initialized the T bit is cleared to 0 in EXR and the I bit is set to 1 in EXR and CCR 2 The reset exception handling vector address is read and transferred t...

Page 104: ...re enabled in interrupt control mode 2 Trace mode is not activated in interrupt control mode 0 irrespective of the state of the T bit For details of interrupt control modes see section 5 Interrupt Con...

Page 105: ...highest priority interrupt Interrupts are controlled by the interrupt controller The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority ma...

Page 106: ...e status of CCR and EXR after execution of trap instruction exception handling Table 4 5 Status of CCR and EXR after Trap Instruction Exception Handling CCR EXR Interrupt Control Mode I UI I2 to I0 T...

Page 107: ...OV L ERn SP Use the following instructions to restore registers POP W Rn or MOV W SP Rn POP L ERn or MOV L SP ERn Setting SP to an odd value may lead to a malfunction Figure 4 5 shows an example of wh...

Page 108: ...Rev 6 00 Oct 28 2004 page 80 of 1016 REJ09B0138 0600H...

Page 109: ...rrupt priorities Eight priority levels can be set for each module for all interrupts except NMI NMI is assigned the highest priority level of 8 and can be accepted at all times Independent vector addr...

Page 110: ...R ISR IPR SYSCR IRQ sense control register IRQ enable register IRQ status register Interrupt priority register System control register Legend Figure 5 1 Block Diagram of Interrupt Controller 5 1 3 Pin...

Page 111: ...register F IPRF R W H 77 H FEC9 Interrupt priority register G IPRG R W H 77 H FECA Interrupt priority register H IPRH R W H 77 H FECB Interrupt priority register I IPRI R W H 77 H FECC Interrupt prio...

Page 112: ...d at falling edge of NMI input Initial value 1 Interrupt request generated at rising edge of NMI input 5 2 2 Interrupt Priority Registers A to K IPRA to IPRK Bit 7 6 5 4 3 2 1 0 IPR6 IPR5 IPR4 IPR2 IP...

Page 113: ...the highest priority level level 7 by setting H 7 When interrupt requests are generated the highest priority interrupt according to the priority levels set in the IPR registers is selected This inter...

Page 114: ...Q7SCA IRQ7SCB to IRQ0 Sense Control A and B IRQ0SCA IRQ0SCB Bits 15 to 0 IRQ7SCB to IRQ0SCB IRQ7SCA to IRQ0SCA Description 0 0 Interrupt request generated at IRQ7 to IRQ0 input low level Initial value...

Page 115: ...interrupts NMI and IRQ7 to IRQ0 and internal interrupts 52 sources 5 3 1 External Interrupts There are nine external interrupts NMI and IRQ7 to IRQ0 Of these NMI and IRQ2 to IRQ0 can be used to restor...

Page 116: ...supporting modules For each on chip supporting module there are flags that indicate the interrupt request status and enable bits that select enabling or disabling of these interrupts If both of these...

Page 117: ...6 H 0068 IPRD2 to 0 Reserved 27 H 006C IPRE6 to 4 ADI A D conversion end A D 28 H 0070 IPRE2 to 0 Reserved 29 30 31 H 0074 H 0078 H 007C TGI0A TGR0A input capture compare match TGI0B TGR0B input captu...

Page 118: ...l 4 56 57 58 59 H 00E0 H 00E4 H 00E8 H 00EC IPRH6 to 4 TGI5A TGR5A input capture compare match TGI5B TGR5B input capture compare match TCI5V overflow 5 TCI5U underflow 5 TPU channel 5 60 61 62 63 H 00...

Page 119: ...control mode NMI interrupts are accepted at all times except in the reset state and the hardware standby state In the case of IRQ interrupts and on chip supporting module interrupts an enable bit is...

Page 120: ...terrupts Selected in Each Interrupt Control Mode 1 Interrupt Mask Bits Interrupt Control Mode I Selected Interrupts 0 0 All interrupts 1 NMI interrupts 2 All interrupts Don t care 2 8 Level Control In...

Page 121: ...module interrupts can be set by means of the I bit in the CPU s CCR Interrupts are enabled when the I bit is cleared to 0 and disabled when set to 1 Figure 5 5 shows a flowchart of the interrupt acce...

Page 122: ...n status Interrupt generated NMI IRQ0 IRQ1 TEI2 I 0 Save PC and CCR I 1 Read vector address Branch to interrupt handling routine Yes No Yes Yes Yes No No No Yes Yes No Hold pending Figure 5 5 Flowchar...

Page 123: ...rity system shown in table 5 4 is selected 3 Next the priority of the selected interrupt request is compared with the interrupt mask level set in EXR An interrupt request with a priority no higher tha...

Page 124: ...elow Level 7 interrupt Mask level 6 or below Save PC CCR and EXR Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Hold pending Level 1 interrupt Mask level 0...

Page 125: ...peration Interrupt acceptance Interrupt level determination Wait for end of instruction Interrupt request signal Internal address bus Internal read signal Internal write signal Internal data bus 3 1 2...

Page 126: ...er of wait states until executing instruction ends 2 1 to 19 2 SI 1 to 19 2 SI 3 PC CCR EXR stack save 2 SK 3 SK 4 Vector fetch 2 SI 2 SI 5 Instruction fetch 3 2 SI 2 SI 6 Internal processing 4 2 2 To...

Page 127: ...for the higher priority interrupt and the lower priority interrupt will be ignored The same also applies when an interrupt source flag is cleared Figure 5 8 shows an example in which the TGIEA bit in...

Page 128: ...leted With the EEPMOV W instruction if an interrupt request is issued during the transfer interrupt exception handling starts at a break in the transfer cycle The PC value saved on the stack in this c...

Page 129: ...terrupt source constituting that DMAC activation source is not a DTC activation source or CPU interrupt source For interrupt sources other than interrupts managed by the DMAC it is possible to select...

Page 130: ...ERA to DTCERF in the DTC and the DISEL bit of MRB in the DTC Table 5 11 Interrupt Source Selection and Clearing Control Settings DMAC DTC Interrupt Source Selection Clearing Control DTA DTCE DISEL DMA...

Page 131: ...or areas 0 to 7 8 bit access or 16 bit access can be selected for each area 2 state access or 3 state access can be selected for each area Program wait states can be inserted for each area DRAM interf...

Page 132: ...Rev 6 00 Oct 28 2004 page 104 of 1016 REJ09B0138 0600H Other features Refresh counter refresh timer can be used as an interval timer External bus release function...

Page 133: ...CS7 External bus control signals BREQ BACK BREQO Internal control signals Wait controller WCRH WCRL Bus mode signal DRAM controller RTCNT RTCOR DRAMCR MCR Bus arbiter CPU bus request signal DTC bus r...

Page 134: ...Chip select 3 row address strobe 3 CS3 Output Strobe signal indicating that area 3 is selected DRAM row address strobe signal when area 3 is in DRAM space Chip select 4 row address strobe 4 CS4 Outpu...

Page 135: ...FED1 Wait control register H WCRH R W H FF Retained H FED2 Wait control register L WCRL R W H FF Retained H FED3 Bus control register H BCRH R W H D0 Retained H FED4 Bus control register L BCRL R W H...

Page 136: ...emory space The bus width for on chip memory and internal I O registers is fixed regardless of the settings in ABWCR After a power on reset and in hardware standby mode ABWCR is initialized to H FF in...

Page 137: ...s of the settings in ASTCR ASTCR is initialized to H FF by a power on reset and in hardware standby mode It is not initialized by a manual reset or in software standby mode Note Manual reset is only s...

Page 138: ...states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1 Bit 7 W71 Bit 6 W70 Description 0 0 Program wait not inserted when external space area 7 is accessed 1 1 progra...

Page 139: ...Bit 0 W40 Description 0 0 Program wait not inserted when external space area 4 is accessed 1 1 program wait state inserted when external space area 4 is accessed 1 0 2 program wait states inserted wh...

Page 140: ...is accessed while the AST1 bit in ASTCR is set to 1 Bit 3 W11 Bit 2 W10 Description 0 0 Program wait not inserted when external space area 1 is accessed 1 1 program wait state inserted when external...

Page 141: ...escription 0 Idle cycle not inserted in case of successive external read cycles in different areas 1 Idle cycle inserted in case of successive external read cycles in different areas Initial value Bit...

Page 142: ...the PF2 pin can be used as an I O port BREQO or WAIT 6 2 5 Bus Control Register L BCRL Bit 7 6 5 4 3 2 1 0 BRLE BREQOE EAE LCASS DDS WDBE WAITE Initial value 0 0 1 1 1 1 0 0 R W R W R W R W R W R W R...

Page 143: ...2 Addresses H 010000 to H 01FFFF are in the H8S 2357 Addresses H 010000 to H 03FFFF are in the H8S 2398 Bit 4 LCAS Select LCASS Write 0 to this bit when using the DRAM interface LCAS pin used for 2 CA...

Page 144: ...set or in software standby mode Note Manual reset is only supported in the H8S 2357 ZTAT Bit 7 TP Cycle Control TPC Selects whether a 1 state or 2 state precharge cycle TP is to be used when areas 2 t...

Page 145: ...23 to A8 used for comparison When 16 bit access space is designated Row address A23 to A9 used for comparison 1 9 bit shift When 8 bit access space is designated Row address A23 to A9 used for compari...

Page 146: ...1 Refresh control is performed Bit 6 RAS CAS Wait RCW Controls wait state insertion in DRAM interface CAS before RAS refreshing Bit 6 RCW Description 0 Wait state insertion in CAS before RAS refreshin...

Page 147: ...ion 0 0 0 Count operation disabled Initial value 1 Count uses 2 1 0 Count uses 8 1 Count uses 32 1 0 0 Count uses 128 1 Count uses 512 1 0 Count uses 2048 1 Count uses 4096 6 2 8 Refresh Timer Counter...

Page 148: ...table register that sets the period for compare match operations with RTCNT The values of RTCOR and RTCNT are constantly compared and if they match the CMF flag in DRAMCR is set to 1 and RTCNT is clea...

Page 149: ...rnal space in area units Figure 6 2 shows an outline of the memory map Chip select signals CS0 to CS7 can be output for each area Area 0 2 Mbytes H 000000 H FFFFFF H 1FFFFF H 200000 Area 1 2 Mbytes H...

Page 150: ...et Number of Access States Two or three access states can be selected with ASTCR An area for which 2 state access is selected functions as a 2 state access space and an area for which 3 state access i...

Page 151: ...ce In ROM enabled expansion mode the space excluding on chip ROM is external space When area 0 external space is accessed the CS0 signal can be output Either basic bus interface or burst ROM interface...

Page 152: ...led expansion mode the CS0 pin is placed in the output state after a power on reset Pins CS1 to CS7 are placed in the input state after a power on reset and so the corresponding DDR should be set to 1...

Page 153: ...s used according to the bus specifications for the area being accessed 8 bit access space or 16 bit access space and the data size 8 Bit Access Space Figure 6 4 illustrates data alignment control for...

Page 154: ...ne byte or one word and a longword transfer instruction is executed as two word transfer instructions In byte access whether the upper or lower data bus is used is determined by whether the address is...

Page 155: ...pper half of the data bus and the LWR signal for the lower half Table 6 4 Data Buses Used and Valid Strobes Area Access Size Read Write Address Valid Strobe Upper Data Bus D15 to D8 Lower data bus D7...

Page 156: ...ess space When an 8 bit access space is accessed the upper half D15 to D8 of the data bus is used The LWR pin is fixed high Wait states cannot be inserted Bus cycle T1 T2 Address bus CSn AS RD D15 to...

Page 157: ...When an 8 bit access space is accessed the upper half D15 to D8 of the data bus is used The LWR pin is fixed high Wait states can be inserted Bus cycle T1 T2 Address bus CSn AS RD D15 to D8 Valid D7...

Page 158: ...cessed the upper half D15 to D8 of the data bus is used for the even address and the lower half D7 to D0 for the odd address Wait states cannot be inserted Bus cycle T1 T2 Address bus CSn AS RD D15 to...

Page 159: ...9B0138 0600H Bus cycle T1 T2 Address bus CSn AS RD D15 to D8 Invalid D7 to D0 Valid Read HWR LWR D15 to D8 High impedance D7 to D0 Valid Write Note n 0 to 7 High Figure 6 9 Bus Timing for 16 Bit 2 Sta...

Page 160: ...2 of 1016 REJ09B0138 0600H Bus cycle T1 T2 Address bus CSn AS RD D15 to D8 Valid D7 to D0 Valid Read HWR LWR D15 to D8 Valid D7 to D0 Valid Write Note n 0 to 7 Figure 6 10 Bus Timing for 16 Bit 2 Stat...

Page 161: ...cessed the upper half D15 to D8 of the data bus is used for the even address and the lower half D7 to D0 for the odd address Wait states can be inserted Bus cycle T1 T2 Address bus CSn AS RD D15 to D8...

Page 162: ...0138 0600H Bus cycle T1 T2 Address bus CSn AS RD D15 to D8 Invalid D7 to D0 Valid Read HWR LWR D15 to D8 High impedance D7 to D0 Valid Write High Note n 0 to 7 T3 Figure 6 12 Bus Timing for 16 Bit 3 S...

Page 163: ...of 1016 REJ09B0138 0600H Bus cycle T1 T2 Address bus CSn AS RD D15 to D8 Valid D7 to D0 Valid Read HWR LWR D15 to D8 Valid D7 to D0 Valid Write Note n 0 to 7 T3 Figure 6 13 Bus Timing for 16 Bit 3 Sta...

Page 164: ...ndividual area basis in 3 state access space according to the settings of WCRH and WCRL Pin Wait Insertion Setting the WAITE bit in BCRL to 1 enables wait insertion by means of the WAIT pin Program wa...

Page 165: ...WAIT pin sampling WAIT Data bus T2 Tw Tw Tw T3 By WAIT pin Figure 6 14 Example of Wait State Insertion Timing The settings after a power on reset are 3 state access 3 program wait state insertion and...

Page 166: ...multiplexing the size of the shift of the row address is selected with bits MXC1 and MXC0 in MCR Table 6 6 shows the relation between the settings of MXC1 and MXC0 and the shift size Table 6 6 Addres...

Page 167: ...strobe 2 Output Row address strobe when area 2 is designated as DRAM space CS3 RAS3 Row address strobe 3 Output Row address strobe when area 3 is designated as DRAM space CS4 RAS4 Row address strobe 4...

Page 168: ...ait insertion and do not affect the number of access states When the corresponding bit in ASTCR is cleared to 0 wait states cannot be inserted in the DRAM access cycle The 4 states of the basic timing...

Page 169: ...R WE Note n 2 to 5 Figure 6 16 Timing with Two Precharge States 6 5 8 Wait Control There are two ways of inserting wait states in a DRAM access cycle program wait insertion and pin wait insertion usin...

Page 170: ...insertion timing By program wait Tp Address bus CSn RAS CAS Data bus Read data Read CAS Write data Write Notes indicates the timing of WAIT pin sampling WAIT Data bus Tr Tc1 Tw Tw Tc2 By WAIT pin n 2...

Page 171: ...onnection When only DRAM with a 8 configuration is connected set the CW2 bit to 1 in MCR Tp CSn RAS Byte control A23 to A0 Tr Tc1 Tc2 Row CAS LCAS HWR WE Column Note n 2 to 5 Figure 6 18 2 CAS System...

Page 172: ...age Mode Operation Timing Figure 6 20 shows the operation timing for burst access When there are consecutive access cycles for DRAM space the CAS signal and column address output cycles two states con...

Page 173: ...the RCDM bit in MCR to 1 If access to DRAM space is interrupted and another space is accessed the RAS signal is held low during the access to the other space and burst access is performed if the row a...

Page 174: ...nal goes high again Burst operation is only performed if DRAM space is continuous Figure 6 22 shows an example of the timing in RAS up mode In the case of burst ROM space access the RAS signal is not...

Page 175: ...ame time RTCNT is reset and starts counting again from H 00 Refreshing is thus repeated at fixed intervals determined by RTCOR and bits CKS2 to CKS0 Set a value in RTCOR and bits CKS2 to CKS0 that wil...

Page 176: ...1 RLW1 0 RLW0 1 Self Refreshing A self refresh mode battery backup mode is provided for DRAM as a kind of standby mode In this mode refresh timing and refresh addresses are generated within the DRAM...

Page 177: ...is accessed in DMAC single address mode at the same time whether or not burst access is to be performed is selected 6 6 1 When DDS 1 Burst access is performed by determining the address only irrespect...

Page 178: ...CK D15 to D0 A23 to A0 Tr Tc1 Tc2 Row Column CAS UCAS LCAS LCAS Note n 2 to 5 Figure 6 29 DACK Output Timing when DDS 0 Example of DRAM Access 6 7 Burst ROM Interface 6 7 1 Overview With the H8S 2357...

Page 179: ...cess space regardless of the setting of the ABW0 bit in ABWCR When the BRSTS0 bit in BCRH is cleared to 0 burst access of up to 4 words is performed when the BRSTS0 bit is set to 1 burst access of up...

Page 180: ...Read data Read data Figure 6 30 b Example of Burst ROM Access Timing When AST0 BRSTS1 0 6 7 3 Wait Control As with the basic bus interface either program wait insertion or pin wait insertion using the...

Page 181: ...to 1 an idle cycle is inserted at the start of the second read cycle This is enabled in advanced mode Figure 6 31 shows an example of the operation in this case In this example bus cycle A is a read...

Page 182: ...and bus cycle B is a CPU write cycle In a an idle cycle is not inserted and a collision occurs in cycle B between the read data from ROM and the CPU write data In b an idle cycle is inserted and a da...

Page 183: ...bus RD Bus cycle A T2 T3 T1 T2 Bus cycle B Possibility of overlap between CS area B and RD T1 Address bus Bus cycle A T2 T3 TI T1 Bus cycle B T2 CS area A CS area B RD CS area A CS area B a Idle cycle...

Page 184: ...TI T1 T2 T3 TcI Tc2 Tc1 EXTAL Address RD RAS CAS LCAS Data bus DRAM space read External read DRAM space read Idle cycle Figure 6 35 a Example of Idle Cycle Operation in RAS Down Mode ICIS1 1 Tp Tr Tc1...

Page 185: ...ows pin states in an idle cycle Table 6 8 Pin States in Idle Cycle Pins Pin State A23 to A0 Contents of next bus cycle D15 to D0 High impedance CSn 2 High 1 CAS High AS High RD High HWR High LWR High...

Page 186: ...ion is used if an external write or DMA single address mode transfer continues for 2 states or longer and there is an internal access next only an external write is executed in the first state but fro...

Page 187: ...nternal bus master wants to make an external access it temporarily defers activation of the bus cycle and waits for the bus request from the external bus master to be dropped Even if a refresh request...

Page 188: ...shows pin states in the external bus released state Table 6 9 Pin States in Bus Released State Pins Pin State A23 to A0 High impedance D15 to D0 High impedance CSn 1 High impedance CAS High impedance...

Page 189: ...t end of CPU read cycle releasing bus to external bus master BREQ pin state is still sampled in external bus released state High level of BREQ pin is sampled BACK pin is driven high ending bus release...

Page 190: ...to the bus master making the request If there are bus requests from more than one bus master the bus request acknowledge signal is sent to the one with the highest priority When a bus master receives...

Page 191: ...transfers the bus immediately DTC The DTC sends the bus arbiter a request for the bus when an activation request is generated The DTC can release the bus after a vector read a register information rea...

Page 192: ...executing bus cycle is discontinued In a manual reset the bus controller s registers and internal state are maintained and an executing external bus cycle is completed In this case WAIT input is ignor...

Page 193: ...fer can be performed in one bus cycle Choice of sequential mode idle mode or repeat mode for dual address mode and single address mode Full address mode Maximum of 2 channels can be used Transfer sour...

Page 194: ...ND1B Control logic DMAWER DMACR1B DMACR1A DMACR0B DMACR0A DMATCR DMABCR Data buffer Internal data bus MAR0A IOAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A IOAR1A ETCR1A MAR1B IOAR1B ETCR1B Legend DMA write e...

Page 195: ...uted for one transfer request Memory address fixed 1 to 65 536 transfers Repeat mode 1 byte or 1 word transfer executed for one transfer request Memory address incremented decremented by 1 or 2 After...

Page 196: ...steal transfer Auto request 24 24 External request 1 byte or 1 word transfer executed for one transfer request 1 to 65 536 transfers External request Block transfer mode Specified block size transfer...

Page 197: ...tically sets the corresponding port to output functioning as a DACK pin With regard to the TEND pins whether or not the corresponding port is used as a TEND pin can be specified by means of a register...

Page 198: ...fined H FEF0 16 bits I O address register 1A IOAR1A R W Undefined H FEF4 16 bits Transfer count register 1A ETCR1A R W Undefined H FEF6 16 bits Memory address register 1B MAR1B R W Undefined H FEF8 16...

Page 199: ...Specifies transfer source transfer destination address Specifies transfer destination transfer source address Specifies number of transfers Specifies transfer size mode activation source etc Specifies...

Page 200: ...byte or word transfer is executed so that the address specified by MAR is constantly updated For details see section 7 2 4 DMA Control Register DMACR MAR is not initialized by a reset or in standby m...

Page 201: ...is performed and when the count reaches H 0000 the DTE bit in DMABCR is cleared and transfer ends 2 Repeat Mode Transfer Number Storage Bit 15 14 13 12 11 10 9 8 ETCRH Initial value R W R W R W R W R...

Page 202: ...ted nor decremented Bit 6 DTID Description 0 MAR is incremented after a data transfer Initial value When DTSZ 0 MAR is incremented by 1 after a transfer When DTSZ 1 MAR is incremented by 2 after a tra...

Page 203: ...on source There are some differences in activation sources for channel A and for channel B Channel A Bit 3 DTF3 Bit 2 DTF2 Bit 1 DTF1 Bit 0 DTF0 Description 0 0 0 0 Initial value 1 Activated by A D co...

Page 204: ...vated by TPU channel 0 compare match input capture A interrupt 1 Activated by TPU channel 1 compare match input capture A interrupt 1 0 Activated by TPU channel 2 compare match input capture A interru...

Page 205: ...cifies whether channel 1 is to be used in short address mode or full address mode Bit 15 FAE1 Description 0 Short address mode Initial value 1 Full address mode In short address mode channels 1A and 1...

Page 206: ...t source selected by the data transfer factor setting issues an interrupt request to the CPU or DTC regardless of the DTA bit setting Bit 11 Data Transfer Acknowledge 1B DTA1B Enables or disables clea...

Page 207: ...g cleared to 0 are as follows When initialization is performed When the specified number of transfers have been completed in a transfer mode other than repeat mode When 0 is written to the DTE bit to...

Page 208: ...r and address register again and then setting the DTE bit to 1 Bit 3 Data Transfer Interrupt Enable 1B DTIE1B Enables or disables the channel 1B transfer end interrupt Bit 3 DTIE1B Description 0 Trans...

Page 209: ...ess register and MARB as the destination address register MAR is composed of two 16 bit registers MARH and MARL The upper 8 bits of MARH are reserved they are always read as 0 and cannot be modified M...

Page 210: ...7 6 5 4 3 2 1 0 ETCRAL Initial value R W R W R W R W R W R W R W R W R W Undefined ETCRB Block Transfer Counter Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETCRB Initial value R W R W R W R W R W R W R...

Page 211: ...ze DTSZ Selects the size of data to be transferred at one time Bit 15 DTSZ Description 0 Byte size transfer Initial value 1 Word size transfer Bit 14 Source Address Increment Decrement SAID Bit 13 Sou...

Page 212: ...er destination address register MARB is to be incremented decremented or left unchanged when data transfer is performed Bit 6 DAID Bit 5 DAIDE Description 0 0 MARB is fixed Initial value 1 MARB is inc...

Page 213: ...Activated by TPU channel 0 compare match input capture A interrupt 1 Activated by TPU channel 1 compare match input capture A interrupt 1 0 Activated by TPU channel 2 compare match input capture A in...

Page 214: ...ized to H 0000 by a reset and in standby mode Bit 15 Full Address Enable 1 FAE1 Specifies whether channel 1 is to be used in short address mode or full address mode In full address mode channels 1A an...

Page 215: ...rrupt source at time of DMA transfer is disabled Initial value 1 Clearing of selected internal interrupt source at time of DMA transfer is enabled Bit 9 Data Transfer Acknowledge 0 DTA0 Enables or dis...

Page 216: ...as indicating the end of a transfer and issues a transfer end interrupt request to the CPU The conditions for the DTE bit being cleared to 0 are as follows When initialization is performed When the s...

Page 217: ...Bit 1 DTIE0B Description 0 Transfer break interrupt disabled Initial value 1 Transfer break interrupt enabled Bits 2 and 0 Data Transfer End Interrupt Enable A DTIEA These bits enable or disable an in...

Page 218: ...channel 0A The address register and count register area is re set by the first DTC transfer then the control register area is re set by the second DTC chain transfer When re setting the control regist...

Page 219: ...nd bit 4 in DMATCR Bit 1 WE0B Description 0 Writes to all bits in DMACR0B bits 9 5 and 1 in DMABCR and bit 4 in DMATCR are disabled Initial value 1 Writes to all bits in DMACR0B bits 9 5 and 1 in DMAB...

Page 220: ...fer End Enable 1 TEE1 Enables or disables transfer end pin 1 TEND1 output Bit 5 TEE1 Description 0 TEND1 pin output disabled Initial value 1 TEND1 pin output enabled Bit 4 Transfer End Enable 0 TEE0 E...

Page 221: ...ter that performs module stop mode control When the MSTP15 bit in MSTPCR is set to 1 the DMAC operation stops at the end of the bus cycle and a transition is made to module stop mode For details see s...

Page 222: ...upt External request Up to 4 channels can operate independently External request applies to channel B only Single address mode applies to channel B only Modes 1 2 and 3 can also be specified for singl...

Page 223: ...vice one byte or one word at a time Unlike dual address mode source and destination accesses are performed in parallel Therefore either the source or the destination is an external device which can be...

Page 224: ...23 0 MAR Source address register Destination address register Start address of transfer destination or transfer source Incremented decremented every transfer 23 0 IOAR 15 H FF Destination address reg...

Page 225: ...bits in ETCR ETCR is decremented by 1 each time a transfer is executed and when its value reaches H 0000 the DTE bit is cleared and transfer ends If the DTIE bit is set to 1 at this time an interrupt...

Page 226: ...DTA bit 2 Set the transfer source address and transfer destination address in MAR and IOAR 3 Set the number of transfers in ETCR 4 Set each bit in DMACR Set the transfer data size with the DTSZ bit Sp...

Page 227: ...nsfer destination or transfer source Fixed 23 0 IOAR 15 H FF Destination address register Source address register Start address of transfer source or transfer destination Fixed 0 15 ETCR Transfer coun...

Page 228: ...t Figure 7 6 shows an example of the setting procedure for idle mode Idle mode setting Set DMABCRH Set transfer source and transfer destination addresses Set number of transfers Set DMACR Read DMABCRL...

Page 229: ...ress register Start address of transfer source or transfer destination Fixed 0 ETCRH 7 0 ETCRL 7 Holds number of transfers Transfer counter Number of transfers Number of transfers Fixed Decremented ev...

Page 230: ...after that terminated when the DTE bit was cleared Figure 7 7 illustrates operation in repeat mode Address T Address B Transfer IOAR 1 byte or word transfer performed in response to 1 transfer reques...

Page 231: ...nterrupt clearing with the DTA bit 2 Set the transfer source address and transfer destination address in MAR and IOAR 3 Set the number of transfers in both ETCRH and ETCRL 4 Set each bit in DMACR Set...

Page 232: ...DTDIR 1 Initial Setting Operation 23 0 MAR Source address register Destination address register Start address of transfer destination or transfer source DACK pin Write strobe Read strobe Set automati...

Page 233: ...e when sequential mode is specified Address T Address B Transfer DACK 1 byte or word transfer performed in response to 1 transfer request Legend Address T L Address B L 1 DTID 2DTSZ N 1 Where L Value...

Page 234: ...nternal interrupt clearing with the DTA bit 2 Set the transfer source address transfer destination address in MAR 3 Set the number of transfers in ETCR 4 Set each bit in DMACR Set the transfer data si...

Page 235: ...ation address register Start address of transfer destination Incremented decremented every transfer or fixed 0 15 ETCRA Transfer counter Number of transfers Decremented every transfer transfer ends wh...

Page 236: ...set in ETCRA TA TB BA BB LA LB N Figure 7 11 Operation in Normal Mode Transfer requests activation sources are external requests and auto requests With auto request the DMAC is only activated by regis...

Page 237: ...ansfer source address in MARA and the transfer destination address in MARB 3 Set the number of transfers in ETCRA 4 Set each bit in DMACRA and DMACRB Set the transfer data size with the DTSZ bit Speci...

Page 238: ...transfer destination Incremented decremented every transfer or fixed 0 ETCRAH 7 0 ETCRAL 7 Holds block size Block size counter Block size Block size Fixed Decremented every transfer ETCRH value copied...

Page 239: ...Consecutive transfer of M bytes or words is performed in response to one request Legend Address Address Address Address Where LA LB LA SAIDE 1 SAID 2DTSZ M N 1 LB DAIDE 1 DAID 2DTSZ N 1 Value set in...

Page 240: ...e 7 14 Operation in Block Transfer Mode BLKDIR 1 ETCRAL is decremented by 1 each time a byte or word transfer is performed In response to a single transfer request burst transfer is performed until th...

Page 241: ...AID 2DTSZ ETCRAH MARA MARA SAIDE 1 SAID 2DTSZ ETCRAH No Yes No Yes No Yes No Yes Clear DTE bit to 0 to end transfer Figure 7 15 Operation Flow in Block Transfer Mode Transfer requests activation sourc...

Page 242: ...ers in ETCRB 4 Set each bit in DMACRA and DMACRB Set the transfer data size with the DTSZ bit Specify whether MARA is to be incremented decremented or fixed with the SAID and SAIDE bits Set the BLKE b...

Page 243: ...the request independently of the interrupt controller Consequently interrupt controller priority settings are not accepted If the DMAC is activated by a CPU interrupt source or an interrupt source th...

Page 244: ...d by register setting only and transfer continues to the end With auto request activation cycle steal mode or burst mode can be selected In cycle steal mode the DMAC releases the bus to another bus ma...

Page 245: ...robe For details of bus cycles see section 7 5 11 DMAC Bus Cycles Single Address Mode Do not specify internal space for transfer addresses in single address mode 7 5 9 Basic DMAC Bus Cycles An example...

Page 246: ...A write DMA dead DMA read DMA write DMA read DMA write Bus release Bus release Bus release Figure 7 19 Example of Short Address Mode Transfer A one byte or one word transfer is performed for one trans...

Page 247: ...ead Address bus RD LWR TEND HWR Bus release Last transfer cycle DMA write DMA read DMA write DMA read DMA write DMA dead Bus release Bus release Bus release Figure 7 20 Example of Full Address Mode Cy...

Page 248: ...sfer end cycle the cycle in which the transfer counter reaches 0 a one state DMA dead cycle is inserted after the DMA write cycle If a request from another higher priority channel is generated after b...

Page 249: ...e DMA read DMA write DMA dead DMA read DMA write DMA read DMA write DMA dead Bus release Bus release Figure 7 22 Example of Full Address Mode Block Transfer Mode Transfer A one block transfer is perfo...

Page 250: ...control Channel Write Idle Transfer source Request Minimum of 2 cycles 1 3 2 4 6 5 7 Acceptance resumes Acceptance resumes DMA write Bus release DMA read DMA write Bus release Request Minimum of 2 cy...

Page 251: ...resumes DMA dead 1 block transfer Idle Dead Dead DMA write Bus release DMA read DMA write DMA dead Bus release Transfer source Transfer destination Request clear period Minimun of 2 cycles Request Ac...

Page 252: ...DREQ Idle Write Idle Bus release DMA control Channel Write Idle Transfer source Bus release DMA read DMA write Bus release Request Minimum of 2 cycles 1 3 2 Minimum of 2 cycles 4 6 5 7 Acceptance res...

Page 253: ...6 5 7 Acceptance resumes DMA dead Bus release DMA read DMA right DMA dead Bus release 1 block transfer Idle Dead Dead 1 block transfer Acceptance resumes Request Minimum of 2 cycles Transfer destinati...

Page 254: ...sfer Figure 7 28 shows a transfer example in which TEND output is enabled and word size single address mode transfer read is performed from external 8 bit 2 state access space to an external device DM...

Page 255: ...29 Example of Single Address Mode Byte Write Transfer Figure 7 30 shows a transfer example in which TEND output is enabled and word size single address mode transfer write is performed from an extern...

Page 256: ...d in the DMAC Start of DMA cycle DREQ pin high level sampling on the rising edge of starts When the DREQ pin high level has been sampled acceptance is resumed after the single cycle is completed As in...

Page 257: ...eared at the next bus break and activation is started in the DMAC The DMAC cycle is started Acceptance is resumed after the single cycle is completed As in 1 the DREQ pin low level is sampled on the r...

Page 258: ...level can always be output from the TEND pin if the bus cycle in which a low level is to be output is an external bus cycle However a low level is not output from the TEND pin if the bus cycle in whi...

Page 259: ...that the bus cycle concerned has ended and starts the next operation Therefore DREQ pin sampling is started one state after the start of the DMA write cycle or single address transfer 7 5 13 DMAC Mult...

Page 260: ...lear Request clear Bus release Channel 0A transfer Bus release Channel 0B transfer Channel 1 transfer Bus release Request hold Read Selection Non selection Selection Figure 7 35 Example of Multi Chann...

Page 261: ...de transfer the DMAC discontinues transfer on completion of the 1 byte or 1 word transfer in progress then releases the bus which passes to the CPU The channel on which transfer was interrupted can be...

Page 262: ...e DTE bit is set to 1 again In full address mode the same applies to the DTME bit Figure 7 37 shows the procedure for forcibly terminating DMAC operation by software Forced termination of DMAC Clear D...

Page 263: ...opriate setting procedure Clearing full address mode Stop the channel Initialize DMACR Clear FAE bit to 0 Initialization operation halted 1 2 3 1 Clear both the DTE bit and the DTME bit in DMABCRL to...

Page 264: ...er on channel 1 Low Enabling or disabling of each interrupt source is set by means of the DTIE bit for the corresponding channel in DMABCR and interrupts from each source are sent to the interrupt con...

Page 265: ...remented Block size counter ETCR operation decremented in block transfer mode 2 Transfer destination address register MAR operation incremented decremented fixed 2 Transfer destination address registe...

Page 266: ...Medium Speed Mode When the DTA bit is 0 internal interrupt signals specified as DMAC transfer sources are edge detected In medium speed mode the DMAC operates on a medium speed clock while on chip sup...

Page 267: ...utput at the TEND pin Internal address Internal read signal External address HWR LWR Internal write signal TEND Not output DMA read External write by CPU etc DMA write Figure 7 42 Example in Which Low...

Page 268: ...by the CPU as necessary Channel Re Setting To reactivate a number of channels when multiple channels are enabled use exclusive handling of transfer end interrupts and perform DMABCR control bit opera...

Page 269: ...fer modes available Incrementing decrementing and fixing of source and destination addresses can be selected Direct specification of 16 Mbyte address space possible 24 bit transfer source and destinat...

Page 270: ...g speed Note When the DTC is used the RAME bit in SYSCR must be set to 1 Interrupt request Interrupt controller DTC Internal address bus DTC service request Control logic Register information MRA MRB...

Page 271: ...er DAR 2 Undefined 3 DTC transfer count register A CRA 2 Undefined 3 DTC transfer count register B CRB 2 Undefined 3 DTC enable registers DTCER R W H 00 H FF30 to H FF35 DTC vector register DTVECR R W...

Page 272: ...t 7 SM1 Bit 6 SM0 Description 0 SAR is fixed 1 0 SAR is incremented after a transfer by 1 when Sz 0 by 2 when Sz 1 1 SAR is decremented after a transfer by 1 when Sz 0 by 2 when Sz 1 Bits 5 and 4 Dest...

Page 273: ...ata transfers can be performed consecutively in response to a single transfer request In data transfer with CHNE set to 1 determination of the end of the specified number of transfers clearing of the...

Page 274: ...de fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined R W CRAH CRAL CRA is a 16 bit register that desi...

Page 275: ...the specified number of transfers have ended 1 DTC activation by this interrupt is enabled Holding condition When the DISEL bit is 0 and the specified number of transfers have not ended n 7 to 0 A DTC...

Page 276: ...pressed as H 0400 vector number 1 1 indicates a one bit left shift For example when DTVEC6 to DTVEC0 H 10 the vector address is H 0420 8 2 9 Module Stop Control Register MSTPCR MSTPCRH MSTPCRL Bit 15...

Page 277: ...number of transfers with a single activation Figure 8 2 shows a flowchart of DTC operation Start Read DTC vector Next transfer Read register information Data transfer Write register information Clear...

Page 278: ...e One transfer request transfers one byte or one word Memory addresses are incremented or decremented by 1 or 2 After the specified number of transfers 1 to 256 the initial state resumes and operation...

Page 279: ...Is 1 or when the Specified Number of Transfers Have Ended Software activation The SWDTE bit is cleared to 0 The SWDTE bit remains set to 1 An interrupt is issued to the CPU Interrupt activation The co...

Page 280: ...e if DTVECR is H 10 the vector address is H 0420 The DTC reads the start address of the register information from the vector address set for each activation source and then reads the register informat...

Page 281: ...H 0442 DTCEB4 TGI0C GR0C compare match input capture 34 H 0444 DTCEB3 TGI0D GR0D compare match input capture 35 H 0446 DTCEB2 TGI1A GR1A compare match input capture TPU channel 1 40 H 0450 DTCEB1 TGI...

Page 282: ...nsfer end 0 DMAC 72 H 0490 DTCEE7 DMTEND0B DMAC transfer end 1 73 H 0492 DTCEE6 DMTEND1A DMAC transfer end 2 74 H 0494 DTCEE5 DMTEND1B DMAC transfer end 3 75 H 0496 DTCEE4 RXI0 reception data full 0 S...

Page 283: ...e MRA SAR MRB DAR CRA and CRB registers in that order from the start address of the register information contents of the vector address In the case of chain transfer register information should be loc...

Page 284: ...Table 8 5 lists the register information in normal mode and figure 8 6 shows memory mapping in normal mode Table 8 5 Register Information in Normal Mode Name Abbreviation Function DTC source address...

Page 285: ...00 and therefore CPU interrupts cannot be requested when DISEL 0 Table 8 6 lists the register information in repeat mode and figure 8 7 shows memory mapping in repeat mode Table 8 6 Register Informat...

Page 286: ...ansfers have ended a CPU interrupt is requested Table 8 7 lists the register information in block transfer mode and figure 8 8 shows memory mapping in block transfer mode Table 8 7 Register Informatio...

Page 287: ...ly Figure 8 9 shows the memory map for chain transfer Source Source Destination Destination DTC vector address Register information start address Register information CHNE 1 Register information CHNE...

Page 288: ...or read Transfer information read Transfer information write Data transfer Read Write Figure 8 10 DTC Operation Timing Example in Normal Mode or Repeat Mode Read Write Read Write Data transfer Transfe...

Page 289: ...Table 8 8 DTC Execution Statuses Mode Vector Read I Register Information Read Write J Data Read K Data Write L Internal Operations M Normal 1 6 1 1 3 Repeat 1 6 1 1 3 Block transfer 1 6 N N 3 N Block...

Page 290: ...is requested If the DTC is to continue transferring data set the DTCE bit to 1 Activation by Software The procedure for using the DTC with software activation is as follows 1 Set the MRA MRB SAR DAR C...

Page 291: ...TS 1 Set MRB to chain mode CHNE 1 DISEL 0 Set the data table start address in SAR the NDRH address in DAR and the data table size in CRAH and CRAL CRB can be set to any value 2 Perform settings for tr...

Page 292: ...ion source is generated These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control In the case of activation by software a software activated data transf...

Page 293: ...ave a on chip pull up MOS function and in addition to DR and DDR have a MOS input pull up control register PCR to control the on off state of MOS input pull up Port 3 and port A include an open drain...

Page 294: ...ls 0 and 1 I O pins TMRI0 TMCI0 TMO0 TMRI1 TMCI1 TMO1 and PPG output pins PO7 to PO0 Port 3 6 bit I O port Open drain output capability P35 SCK1 P34 SCK0 P33 RxD1 P32 RxD0 P31 TxD1 P30 TxD0 6 bit I O...

Page 295: ...nput PA4 to PA7 PA4 A20 IRQ4 Address output When DDR 1 address output PA3 A19 to PA0 A16 Address output When DDR 0 after reset input ports When DDR 1 address output I O port Port B 8 bit I O port On c...

Page 296: ...input When WAITE 0 and BREQOE 1 BREQO output When RMTS2 to RMTS0 B 001 to B 011 CW2 0 and LCASS 0 LCAS output PF1 BACK PF0 BREQ When BRLE 0 after reset I O port When BRLE 1 BREQ input BACK output Por...

Page 297: ...P16 I O PO14 output TIOCA2 I O P15 I O PO13 output TIOCB1 I O TCLKC input P14 I O PO12 output TIOCA1 I O P13 I O PO11 output TIOCD0 I O TCLKB input P12 I O PO10 output TIOCC0 I O TCLKA input P11 I O P...

Page 298: ...0DR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W P1DR is an 8 bit readable writable register that stores output data for the port 1 pins P17 to P10 P1DR is initialized to H 00 by...

Page 299: ...to IOB0 in TIOR2 bits CCLR1 and CCLR0 in TCR2 bits TPSC2 to TPSC0 in TCR0 and TCR5 bit NDER15 in NDERH and bit P17DDR TPU Channel 2 Setting Table Below 1 Table Below 2 P17DDR 0 1 1 NDER15 0 1 Pin func...

Page 300: ...DDR TPU Channel 2 Setting Table Below 1 Table Below 2 P16DDR 0 1 1 NDER14 0 1 Pin function TIOCA2 output P16 input P16 output PO14 output TIOCA2 input 1 Note 1 TIOCA2 input when MD3 to MD0 B 0000 B 01...

Page 301: ...1 1 NDER13 0 1 Pin function TIOCB1 output P15 input P15 output PO13 output TIOCB1 input 1 TCLKC input 2 Notes 1 TIOCB1 input when MD3 to MD0 B 0000 B 01 and IOB3 to IOB0 B 10 2 TCLKC input when the se...

Page 302: ...nel 1 Setting Table Below 1 Table Below 2 P14DDR 0 1 1 NDER12 0 1 Pin function TIOCA1 output P14 input P14 output PO12 output TIOCA1 input 1 Note 1 TIOCA1 input when MD3 to MD0 B 0000 B 01 IOA3 to IOA...

Page 303: ...able Below 1 Table Below 2 P13DDR 0 1 1 NDER11 0 1 Pin function TIOCD0 output P13 input P13 output PO11 output TIOCD0 input 1 TCLKB input 2 Notes 1 TIOCD0 input when MD3 to MD0 B 0000 IOD3 to IOD0 B 1...

Page 304: ...OCC0 output P12 input P12 output PO10 output TIOCC0 input 1 TCLKA input 2 Notes 1 TIOCC0 input when MD3 to MD0 B 0000 and IOC3 to IOC0 B 10 2 TCLKA input when the setting for TCR0 to TCR5 is TPSC2 to...

Page 305: ...it SAE1 in DMABCRH and bit P11DDR SAE1 0 1 TPU Channel 0 Setting Table Below 1 Table Below 2 P11DDR 0 1 1 NDER9 0 1 Pin function TIOCB0 output P11 input P11 output PO9 output DACK1 output TIOCB0 input...

Page 306: ...DR SAE0 0 1 TPU Channel 0 Setting Table Below 1 Table Below 2 P10DDR 0 1 1 NDER8 0 1 Pin function TIOCA0 output P10 input P10 output PO8 output DACK0 output TIOCA0 input 1 Note 1 TIOCA0 input when MD3...

Page 307: ...1 I O PO1 output TIOCB3 I O P20 I O PO0 output TIOCA3 I O Port 2 Port 2 pins Figure 9 2 Port 2 Pin Functions 9 3 2 Register Configuration Table 9 4 shows the port 2 register configuration Table 9 4 Po...

Page 308: ...re standby mode It retains its prior state after a manual reset and in software standby mode Note Manual reset is only supported in the H8S 2357 ZTAT Port 2 Register PORT2 Bit 7 6 5 4 3 2 1 0 P27 P26...

Page 309: ...ation of the TPU channel 5 setting by bits MD3 to MD0 in TMDR5 bits IOB3 to IOB0 in TIOR5 bits CCLR1 and CCLR0 in TCR5 bit NDER7 in NDERL bits OS3 to OS0 in TCSR1 and bit P27DDR OS3 to OS0 All 0 Any 1...

Page 310: ...OS3 to OS0 All 0 Any 1 TPU Channel 5 Setting Table Below 1 Table Below 2 P26DDR 0 1 1 NDER6 0 1 Pin function TIOCA5 output P26 input P26 output PO6 output TMO0 output TIOCA5 input 1 Note 1 TIOCA5 inp...

Page 311: ...bits IOB3 to IOB0 in TIOR4 bits CCLR1 and CCLR0 in TCR4 bit NDER5 in NDERL and bit P25DDR TPU Channel 4 Setting Table Below 1 Table Below 2 P25DDR 0 1 1 NDER5 0 1 Pin function TIOCB4 output P25 input...

Page 312: ...CCLR0 in TCR4 bit NDER4 in NDERL and bit P24DDR TPU Channel 4 Setting Table Below 1 Table Below 2 P24DDR 0 1 1 NDER4 0 1 Pin function TIOCA4 output P24 input P24 output PO4 output TIOCA4 input 1 TMRI1...

Page 313: ...bits IOD3 to IOD0 in TIOR3L bits CCLR2 to CCLR0 in TCR3 bit NDER3 in NDERL and bit P23DDR TPU Channel 3 Setting Table Below 1 Table Below 2 P23DDR 0 1 1 NDER3 0 1 Pin function TIOCD3 output P23 input...

Page 314: ...and bit P22DDR TPU Channel 3 Setting Table Below 1 Table Below 2 P22DDR 0 1 1 NDER2 0 1 Pin function TIOCC3 output P22 input P22 output PO2 output TIOCC3 input 1 TMRI0 input Note 1 TIOCC3 input when...

Page 315: ...t NDER1 in NDERL and bit P21DDR TPU Channel 3 Setting Table Below 1 Table Below 2 P21DDR 0 1 1 NDER1 0 1 Pin function TIOCB3 output P21 input P21 output PO1 output TIOCB3 input Note TIOCB3 input when...

Page 316: ...TPU Channel 3 Setting Table Below 1 Table Below 2 P20DDR 0 1 1 NDER0 0 1 Pin function TIOCA3 output P20 input P20 output PO0 output TIOCA3 input 1 Note 1 TIOCA3 input when MD3 to MD0 B 0000 and IOA3...

Page 317: ...R W Initial Value 2 Address 1 Port 3 data direction register P3DDR W H 00 H FEB2 Port 3 data register P3DR R W H 00 H FF62 Port 3 register PORT3 R Undefined H FF52 Port 3 open drain control register...

Page 318: ...AT Port 3 Register PORT3 Bit 7 6 5 4 3 2 1 0 P35 P34 P33 P32 P31 P30 Initial value Undefined Undefined R W R R R R R R Note Determined by state of pins P35 to P30 PORT3 is an 8 bit read only register...

Page 319: ...RxD1 and SCK1 Port 3 pin functions are shown in table 9 7 Table 9 7 Port 3 Pin Functions Pin Selection Method and Pin Functions P35 SCK1 The pin function is switched as shown below according to the co...

Page 320: ...it P32DDR RE 0 1 P32DDR 0 1 Pin function P32 input pin P32 output pin RxD0 input pin Note When P32ODR 1 the pin becomes an NMOS open drain output P31 TxD1 The pin function is switched as shown below a...

Page 321: ...Port 4 pins Port 4 Figure 9 4 Port 4 Pin Functions 9 5 2 Register Configuration Table 9 8 shows the port 4 register configuration Port 4 is an input only port and does not have a data direction regist...

Page 322: ...R R W H 0 H FF64 Port 5 register PORT5 R Undefined H FF54 Notes 1 Lower 16 bits of the address 2 Value of bits 3 to 0 Port 5 Data Direction Register P5DDR Bit 7 6 5 4 3 2 1 0 P53DDR P52DDR P51DDR P50D...

Page 323: ...Port 5 Register PORT5 Bit 7 6 5 4 3 2 1 0 P53 P52 P51 P50 Initial value Undefined Undefined Undefined Undefined R W R R R R Note Determined by state of pins P53 to P50 PORT5 is an 8 bit read only regi...

Page 324: ...ote ADTRG input when TRGS0 TRGS1 1 P52 SCK2 The pin function is switched as shown below according to the combination of bit C A in the SCI2 SMR bits CKE0 and CKE1 in SCR and bit P52DDR CKE1 0 1 C A 0...

Page 325: ...input P65 I O IRQ1 input P64 I O IRQ0 input P63 I O TEND1 output P62 I O DREQ1 input P61 I O TEND0 output P60 I O DREQ0 input Port 6 pins Pin functions in mode 7 P67 input IRQ3 input CS7 output P66 in...

Page 326: ...itial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W P6DR is an 8 bit readable writable register that stores output data for the port 6 pins P67 to P60 P6DR is initialized to H 00 by a powe...

Page 327: ...nput pin CS7 output pin IRQ3 interrupt input pin Note Modes 6 and 7 are provided in the on chip ROM version only P66 IRQ2 CS6 The pin function is switched as shown below according to bit P66DDR Mode M...

Page 328: ...DERQ1 input P61 TEND0 CS5 The pin function is switched as shown below according to the combination of bit TEE0 in the DMAC DMATCR and bit P61DDR Mode Mode 7 Modes 4 to 6 TEE0 0 1 0 1 P61DDR 0 1 0 1 P...

Page 329: ...A2 A18 PA1 A17 PA0 A16 PA7 input A23 output IRQ7 input PA6 input A22 output IRQ6 input PA5 input A21 output IRQ5 input A20 output A19 output A18 output A17 output A16 output Note Modes 6 and 7 are pro...

Page 330: ...t for the pins of port A PADDR cannot be read if it is an undefined value will be read PADDR is initialized to H 00 by a power on reset and in hardware standby mode It retains its prior state after a...

Page 331: ...are cleared to 0 the pin states are read After a power on reset and in hardware standby mode PORTA contents are determined by the pin states as PADDR and PADR are initialized PORTA retains its prior...

Page 332: ...e bit to 0 makes the pin a CMOS output PAODR is initialized to H 00 by a power on reset and in hardware standby mode It retains its prior state after a manual reset and in software standby mode Note M...

Page 333: ...PADDR 1 When PADDR 0 Port A Figure 9 9 Port A Pin Functions Mode 6 Modes 4 and 5 In modes 4 and 5 the lower 5 bits of port A are designated as address outputs automatically while the upper 3 bits func...

Page 334: ...OS input pull up for that pin The MOS input pull up function is in the off state after a power on reset and in hardware standby mode The prior state is retained after a manual reset and in software st...

Page 335: ...A15 PB6 A14 PB5 A13 PB4 A12 PB3 A11 PB2 A10 PB1 A9 PB0 A8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Note Modes 6 and 7 are provided in the on chip ROM version only input input input input input input input inp...

Page 336: ...rior state after a manual reset and in software standby mode The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high impedance when a transition...

Page 337: ...are initialized PORTB retains its prior state after a manual reset and in software standby mode Note Manual reset is only supported in the H8S 2357 ZTAT Port B MOS Pull Up Control Register PBPCR On Ch...

Page 338: ...I O I O I O I O I O I O I O Figure 9 12 Port B Pin Functions Mode 7 Mode 6 On Chip ROM Version Only In mode 6 port B pins function as address outputs or input ports Input or output can be specified on...

Page 339: ...s on or off on an individual bit basis When a PBDDR bit is cleared to 0 in mode 6 or 7 setting the corresponding PBPCR bit to 1 turns on the MOS input pull up for that pin The MOS input pull up functi...

Page 340: ...ration PC7 A7 PC6 A6 PC5 A5 PC4 A4 PC3 A3 PC2 A2 PC1 A1 PC0 A0 Port C PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Note Modes 6 and 7 are provided in the on chip ROM version only input input input input input inpu...

Page 341: ...prior state after a manual reset and in software standby mode The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high impedance when a transitio...

Page 342: ...are initialized PORTC retains its prior state after a manual reset and in software standby mode Note Manual reset is only supported in the H8S 2357 ZTAT Port C MOS Pull Up Control Register PCPCR On Ch...

Page 343: ...I O I O I O I O I O I O I O I O Figure 9 16 Port C Pin Functions Mode 7 Mode 6 On Chip ROM Version Only In mode 6 port C pins function as address outputs or input ports Input or output can be specifie...

Page 344: ...n or off on an individual bit basis When a PCDDR bit is cleared to 0 in mode 6 or 7 setting the corresponding PCPCR bit to 1 turns on the MOS input pull up for that pin The MOS input pull up function...

Page 345: ...input pull up function that can be controlled by software on chip ROM version only Figure 9 19 shows the port D pin configuration PD7 D15 PD6 D14 PD5 D13 PD4 D12 PD3 D11 PD2 D10 PD1 D9 PD0 D8 Note Mod...

Page 346: ...efined value will be read PDDDR is initialized to H 00 by a power on reset and in hardware standby mode It retains its prior state after a manual reset and in software standby mode Note Manual reset i...

Page 347: ...ins its prior state after a manual reset and in software standby mode Note Manual reset is only supported in the H8S 2357 ZTAT Port D MOS Pull Up Control Register PDPCR On Chip ROM Version Only Bit 7...

Page 348: ...t to 0 makes the pin an input port Port D pin functions in mode 7 are shown in figure 9 20 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Port D I O I O I O I O I O I O I O I O Figure 9 20 Port D Pin Functions Mode...

Page 349: ...ll up for that pin The MOS input pull up function is in the off state after a power on reset and in hardware standby mode The prior state is retained after a manual reset and in software standby mode...

Page 350: ...an be controlled by software on chip ROM version only Figure 9 22 shows the port E pin configuration PE7 D7 PE6 D6 PE5 D5 PE4 D4 PE3 D3 PE2 D2 PE1 D1 PE0 D0 Note Modes 6 and 7 are provided in the on c...

Page 351: ...a power on reset and in hardware standby mode It retains its prior state after a manual reset and in software standby mode Note Manual reset is only supported in the H8S 2357 ZTAT Mode 7 Setting a PE...

Page 352: ...ined by the pin states as PEDDR and PEDR are initialized PORTE retains its prior state after a manual reset and in software standby mode Note Manual reset is only supported in the H8S 2357 ZTAT Port E...

Page 353: ...s Mode 7 Modes 4 to 6 In modes 4 to 6 when 8 bit access is designated and 8 bit bus mode is selected port E pins are automatically designated as I O ports Setting a PEDDR bit to 1 makes the correspond...

Page 354: ...PEPCR bit to 1 turns on the MOS input pull up for that pin The MOS input pull up function is in the off state after a power on reset and in hardware standby mode The prior state is retained after a m...

Page 355: ...t F pin configuration PF7 PF6 AS PF5 RD PF4 HWR PF3 LWR PF2 LCAS WAIT BREQO PF1 BACK PF0 BREQ Port F Port F pins PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Note Modes 6 and 7 are provided in the on chip ROM vers...

Page 356: ...n mode 7 It retains its prior state after a manual reset and in software standby mode The OPE bit in SBYCR is used to select whether the bus control output pins retain their output state or become hig...

Page 357: ...ister PORTF Bit 7 6 5 4 3 2 1 0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Initial value R W R R R R R R R R Note Determined by state of pins PF7 to PF0 PORTF is an 8 bit read only register that shows the pin st...

Page 358: ...input pin PF6 output pin Note Modes 6 and 7 are provided in the on chip ROM version only PF5 RD The pin function is switched as shown below according to the operating mode and bit PF5DDR Operating Mo...

Page 359: ...S0 B 001 to B 011 2 Modes 6 and 7 are provided in the on chip ROM version only PF1 BACK The pin function is switched as shown below according to the combination of the operating mode and bits BRLE and...

Page 360: ...Pin functions in mode 7 Pin functions in modes 4 to 6 PG4 input CS0 output PG3 input CS1 output PG2 input CS2 output PG1 input CS3 output PG0 I O CAS output Port G Figure 9 26 Port G Pin Functions 9...

Page 361: ...1 makes the corresponding port G pin an output port while clearing the bit to 0 makes the pin an input port Modes 4 to 6 Pins PG4 to PG1 function as bus control output pins CS0 to CS3 when the corresp...

Page 362: ...t always be performed on PGDR Bits 7 to 5 are reserved they return an undetermined value if read and cannot be modified If a port G read is performed while PGDDR bits are set to 1 the PGDR values are...

Page 363: ...tput pin Note Modes 6 and 7 are provided in the on chip ROM version only PG2 CS2 The pin function is switched as shown below according to the operating mode and bit PG2DDR Operating Mode Mode 7 Modes...

Page 364: ...Rev 6 00 Oct 28 2004 page 336 of 1016 REJ09B0138 0600H...

Page 365: ...er synchronous operation PWM mode Any PWM output duty can be set Maximum of 15 phase PWM output possible by combination with synchronous operation Buffer operation settable for channels 0 and 3 Input...

Page 366: ...n be generated Channel 0 to 5 compare match A input capture A signals can be used as A D converter conversion start trigger Module stop mode can be set As the initial setting TPU operation is halted R...

Page 367: ...TGR3A TGR3B TGR4A TGR4B TGR5A TGR5B General registers buffer registers TGR0C TGR0D TGR3C TGR3D I O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB...

Page 368: ...put capture TGR5A compare match or input capture PPG trigger TGR0A TGR0B compare match or input capture TGR1A TGR1B compare match or input capture TGR2A TGR2B compare match or input capture TGR3A TGR3...

Page 369: ...s TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Clock input 1 4 16 64 256 1024 4096 TCLKA TCLKB TCLKC TCLKD Input output pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 Interrup...

Page 370: ...O TGR1A input capture input output compare output PWM output pin Input capture out compare match B1 TIOCB1 I O TGR1B input capture input output compare output PWM output pin 2 Input capture out compar...

Page 371: ...register 0C TGR0C R W H FFFF H FFDC Timer general register 0D TGR0D R W H FFFF H FFDE 1 Timer control register 1 TCR1 R W H 00 H FFE0 Timer mode register 1 TMDR1 R W H C0 H FFE1 Timer I O control reg...

Page 372: ...R W H C0 H FE91 Timer I O control register 4 TIOR4 R W H 00 H FE92 Timer interrupt enable register 4 TIER4 R W H 40 H FE94 Timer status register 4 TSR4 R W 2 H C0 H FE95 Timer counter 4 TCNT4 R W H 0...

Page 373: ...R W Channel 1 TCR1 Channel 2 TCR2 Channel 4 TCR4 Channel 5 TCR5 Bit 7 6 5 4 3 2 1 0 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W The TCR reg...

Page 374: ...input capture 2 1 TCNT cleared by counter clearing for another channel performing synchronous clearing synchronous operation 1 Channel Bit 7 Reserved 3 Bit 6 CCLR1 Bit 5 CCLR0 Description 1 2 4 5 0 0...

Page 375: ...rflow underflow of another channel is selected Bits 2 to 0 Time Prescaler 2 to 0 TPSC2 to TPSC0 These bits select the TCNT counter clock The clock source can be selected independently for each channel...

Page 376: ...scription 2 0 0 0 Internal clock counts on 1 Initial value 1 Internal clock counts on 4 1 0 Internal clock counts on 16 1 Internal clock counts on 64 1 0 0 External clock counts on TCLKA pin input 1 E...

Page 377: ...it 0 TPSC0 Description 5 0 0 0 Internal clock counts on 1 Initial value 1 Internal clock counts on 4 1 0 Internal clock counts on 16 1 Internal clock counts on 64 1 0 0 External clock counts on TCLKA...

Page 378: ...lly Initial value 1 TGRB and TGRD used together for buffer operation Bit 4 Buffer Operation A BFA Specifies whether TGRA is to operate in the normal way or TGRA and TGRC are to be used together for bu...

Page 379: ...W R W R W Note When TGRC or TGRD is designated for buffer operation this setting is invalid and the register operates as a buffer register The TIOR registers are 8 bit registers that control the TGR...

Page 380: ...atch 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 0 output at compare match 1 0 output 1 output at compare match 1 Toggle output at compare matc...

Page 381: ...are set to B 000 and 1 is used as the TCNT1 count clock this setting is invalid and input capture is not generated 2 When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register this s...

Page 382: ...care Channel Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 Description 3 0 0 0 0 TGR3B is Output disabled Initial value 1 1 0 1 output compare register Initial output is 0 output 0 output at compare mat...

Page 383: ...ch 1 Toggle output at compare match 1 0 0 1 0 1 TGR3D is input capture register 2 Capture input source is TIOCD3 pin Input capture at rising edge Input capture at falling edge Input capture at both ed...

Page 384: ...ut capture at falling edge Input capture at both edges 1 Capture input source is TGR3C compare match input capture Input capture at generation of TGR3C compare match input capture Don t care Channel B...

Page 385: ...Input capture at both edges 1 Capture input source is channel 1 count clock Input capture at TCNT1 count up count down Don t care Channel Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 Description 0 0 0...

Page 386: ...pture at falling edge Input capture at both edges 1 Capture input source is TGR0A compare match input capture Input capture at generation of channel 0 TGR0A compare match input capture Don t care Chan...

Page 387: ...capture at TCNT4 count up count down Don t care Channel Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 Description 3 0 0 0 0 TGR3C is Output disabled Initial value 1 1 0 1 output compare register 1 Init...

Page 388: ...ut capture at falling edge Input capture at both edges 1 Capture input source is TGR3A compare match input capture Input capture at generation of TGR3A compare match input capture Don t care Channel B...

Page 389: ...isters are initialized to H 40 by a reset and in hardware standby mode Bit 7 A D Conversion Start Request Enable TTGE Enables or disables generation of A D conversion start requests by TGRA input capt...

Page 390: ...TGR Interrupt Enable C TGIEC Enables or disables interrupt requests TGIC by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3 In channels 1 2 4 and 5 bit 2 is reserved It is alway...

Page 391: ...ers are initialized to H C0 by a reset and in hardware standby mode Bit 7 Count Direction Flag TCFD Status flag that shows the direction in which TCNT counts in channels 1 2 4 and 5 In channels 0 and...

Page 392: ...n DTC is 0 When 0 is written to TGFD after reading TGFD 1 1 Setting conditions When TCNT TGRD while TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input captu...

Page 393: ...rred to TGRB by input capture signal while TGRB is functioning as input capture register Bit 0 Input Capture Output Compare Flag A TGFA Status flag that indicates the occurrence of TGRA input capture...

Page 394: ...it 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W The TGR registers are 16 bit registers with a...

Page 395: ...ynchronous operation for the channel 0 to 4 TCNT counters A channel performs synchronous operation when the corresponding bit in TSYR is set to 1 TSYR is initialized to H 00 by a reset and in hardware...

Page 396: ...stop mode control When the MSTP13 bit in MSTPCR is set to 1 TPU operation stops at the end of the bus cycle and a transition is made to module stop mode Registers cannot be read or written to in modu...

Page 397: ...6 bits wide these registers can be read and written to in 16 bit units These registers cannot be read or written to in 8 bit units 16 bit access must always be used An example of 16 bit register acces...

Page 398: ...it register access operation are shown in figures 10 3 to 10 5 Bus interface H Internal data bus L Module data bus TCR Bus master Figure 10 3 8 Bit Register Access Operation Bus Master TCR Upper 8 Bit...

Page 399: ...When TGR is an output compare register When a compare match occurs the value in the buffer register for the relevant channel is transferred to TGR When TGR is an input capture register When input capt...

Page 400: ...nter Set period Start count operation Periodic counter 1 2 4 3 5 Free running counter Start count operation Free running counter 5 1 2 3 4 5 Select output compare register Select the counter clock wit...

Page 401: ...re match is selected as the TCNT clearing source the TCNT counter for the relevant channel performs periodic count operation The TGR register for setting the period is designated as an output compare...

Page 402: ...The set initial value is output at the TIOC pin until the first compare match occurs 2 Set the timing for compare match generation in TGR 3 Set the CST bit in TSTR to 1 to start the count operation F...

Page 403: ...0 1 3 and 4 it is also possible to specify another channel s counter input clock or compare match signal as the input capture source Note When another channel s counter input clock is used as the inpu...

Page 404: ...e been selected as the TIOCA pin input capture input edge falling edge has been selected as the TIOCB pin input capture input edge and counter clearing by TGRB input capture has been designated for TC...

Page 405: ...sponding to the channels to be designated for synchronous operation When the TCNT counter of any of the channels designated for synchronous operation is written to the same value is simultaneously wri...

Page 406: ...138 0600H For details of PWM modes see section 10 4 6 PWM Modes TCNT0 to TCNT2 values H 0000 TIOC0A TIOC1A Time TGR0B Synchronous clearing by TGR0B compare match TGR2A TGR1A TGR2B TGR0A TGR1B TIOC2A F...

Page 407: ...R3C TGR3B TGR3D When TGR is an output compare register When a compare match occurs the value in the buffer register for the corresponding channel is transferred to the timer general register This oper...

Page 408: ...n TGR is an output compare register Figure 10 19 shows an operation example in which PWM mode 1 has been designated for channel 0 and buffer operation has been designated for TGRA and TGRC The setting...

Page 409: ...learing by TGRA input capture has been set for TCNT and both rising and falling edges have been selected as the TIOCA pin input capture input edge As buffer operation has been set when the TCNT value...

Page 410: ...s set for channel 1 or 4 the counter clock setting is invalid and the counter operates independently in phase counting mode Table 10 6 Cascaded Combinations Combination Upper 16 Bits Lower 16 Bits Cha...

Page 411: ...Operation 1 Figure 10 23 illustrates the operation when counting upon TCNT2 overflow underflow has been set for TCNT1 and phase counting mode has been designated for channel 2 TCNT1 is incremented by...

Page 412: ...IOR is performed by means of compare matches Upon counter clearing by a synchronization register compare match the output value of each pin is the initial value set in TIOR If the set values of the cy...

Page 413: ...e register and select the initial value and output value 4 Set the cycle in the TGR selected in 2 and set the duty in the other the TGR 5 Select the PWM mode with bits MD3 to MD0 in TMDR 6 Set the CST...

Page 414: ...e and 0 is set for the initial output value and 1 for the output value of the other TGR registers TGR0A to TGR0D TGR1A to output a 5 phase PWM waveform In this case the value set in TGR1B is used as t...

Page 415: ...TCNT value TGRA H 0000 TIOCA Time TGRB 100 duty TGRB rewritten TGRB rewritten TGRB rewritten Output does not change when cycle register and duty register compare matches occur simultaneously TCNT valu...

Page 416: ...of whether TCNT is counting up or down Table 10 8 shows the correspondence between external clock pins and channels Table 10 8 Phase Counting Mode Clock Input Pins External Clock Pins Channels A Phase...

Page 417: ...ls 2 and 4 TCLKB Channels 1 and 5 TCLKD Channels 2 and 4 Operation High level Up count Low level Low level High level High level Down count Low level High level Low level Legend Rising edge Falling ed...

Page 418: ...t care High level Up count High level Don t care Low level Don t care High level Don t care Low level Down count Legend Rising edge Falling edge Phase counting mode 3 Figure 10 31 shows an example of...

Page 419: ...t care High level Up count High level Down count Low level Don t care High level Don t care Low level Don t care Legend Rising edge Falling edge Phase counting mode 4 Figure 10 32 shows an example of...

Page 420: ...nnel 1 is set to phase counting mode 1 and the encoder pulse A phase and B phase are input to TCLKA and TCLKB Channel 0 operates with TCNT counter clearing by TGR0C compare match TGR0A and TGR0C are u...

Page 421: ...annel 1 TGR1A speed period capture TGR0A speed control period TGR1B position period capture TGR0C position control period TGR0B pulse width capture TGR0D buffer operation Channel 0 TCLKA TCLKB Edge de...

Page 422: ...pt request signals to be enabled or disabled individually When an interrupt request is generated the corresponding status flag in TSR is set to 1 If the corresponding enable disable bit in TIER is set...

Page 423: ...sible Possible TCI2V TCNT2 overflow Not possible Not possible TCI2U TCNT2 underflow Not possible Not possible 3 TGI3A TGR3A input capture compare match Possible Possible TGI3B TGR3B input capture comp...

Page 424: ...s 1 2 4 and 5 10 5 2 DTC DMAC Activation DTC Activation The DTC can be activated by the TGR input capture compare match interrupt for a channel For details see section 8 Data Transfer Controller A tot...

Page 425: ...ternal clock operation and figure 10 35 shows TCNT count timing in external clock operation TCNT TCNT input clock Internal clock N 1 N N 1 N 2 Falling edge Rising edge Figure 10 34 Count Timing in Int...

Page 426: ...the TCNT input clock is generated Figure 10 36 shows output compare output timing TGR TCNT TCNT input clock N N N 1 Compare match signal TIOC pin Figure 10 36 Output Compare Output Timing Input Captur...

Page 427: ...REJ09B0138 0600H TCNT Counter clear signal Compare match signal TGR N N H 0000 Figure 10 38 Counter Clear Timing Compare Match TCNT Counter clear signal Input capture signal TGR N H 0000 N Figure 10...

Page 428: ...gures 10 40 and 10 41 show the timing in buffer operation TGRA TGRB Compare match signal TCNT TGRC TGRD n N N n n 1 Figure 10 40 Buffer Operation Timing Compare Match TGRA TGRB TCNT Input capture sign...

Page 429: ...rrupt request signal timing TGR TCNT TCNT input clock N N N 1 Compare match signal TGF flag TGI interrupt Figure 10 42 TGI Interrupt Timing Compare Match TGF Flag Setting Timing in Case of Input Captu...

Page 430: ...signal timing Figure 10 45 shows the timing for setting of the TCFU flag in TSR by underflow occurrence and TCIU interrupt request signal timing Overflow signal TCNT overflow TCNT input clock H FFFF...

Page 431: ...for status flag clearing by the CPU and figure 10 47 shows the timing for status flag clearing by the DTC or DMAC Status flag Write signal Address TSR address Interrupt request signal TSR write cycle...

Page 432: ...th must be at least 2 5 states Figure 10 48 shows the input clock conditions in phase counting mode Overlap Phase differ ence Phase differ ence Overlap TCLKA TCLKC TCLKB TCLKD Pulse width Pulse width...

Page 433: ...ite signal Address TCNT address TCNT TCNT write cycle T1 T2 N H 0000 Figure 10 49 Contention between TCNT Write and Clear Operations Contention between TCNT Write and Increment Operations If increment...

Page 434: ...address TCNT TGR write cycle T1 T2 N M TGR write data TGR N N 1 Prohibited Figure 10 51 Contention between TGR Write and Compare Match Contention between Buffer Register Write and Compare Match If a...

Page 435: ...ress TGR address TGR TGR read cycle T1 T2 M Internal data bus X M Figure 10 53 Contention between TGR Read and Input Capture Contention between TGR Write and Input Capture If the input capture signal...

Page 436: ...e cycle T1 T2 N TGR N M M Buffer register Buffer register address Figure 10 55 Contention between Buffer Register Write and Input Capture Contention between Overflow Underflow and Counter Clearing If...

Page 437: ...g Prohibited Figure 10 57 Contention between TCNT Write and Overflow Multiplexing of I O Pins In the H8S 2357 Group the TCLKA input pin is multiplexed with the TIOCC0 I O pin the TCLKB input pin with...

Page 438: ...Rev 6 00 Oct 28 2004 page 410 of 1016 REJ09B0138 0600H...

Page 439: ...roups Output trigger signals can be selected in 4 bit groups to provide up to four different 4 bit outputs Selectable output trigger signals Output trigger signals can be selected for each group from...

Page 440: ...register PPG output control register Next data enable register H Next data enable register L Next data register H Next data register L Output data register H Output data register L Internal data bus...

Page 441: ...se output 2 PO2 Output Pulse output 3 PO3 Output Pulse output 4 PO4 Output Group 1 pulse output Pulse output 5 PO5 Output Pulse output 6 PO6 Output Pulse output 7 PO7 Output Pulse output 8 PO8 Output...

Page 442: ...gister L NDRL R W H 00 H FF4D 3 H FF4F Port 1 data direction register P1DDR W H 00 H FEB0 Port 2 data direction register P2DDR W H 00 H FEB1 Module stop control register MSTPCR R W H 3FFF H FF3C Notes...

Page 443: ...ulse output is disabled the bit value is not transferred from NDR to PODR and the output value does not change NDERH and NDERL are each initialized to H 00 by a reset and in hardware standby mode They...

Page 444: ...when the TPU compare match event specified by PCR occurs The NDRH and NDRL addresses differ depending on whether pulse output groups have the same output trigger or different output triggers For deta...

Page 445: ...se output groups 2 and 3 are triggered by different compare match events the address of the upper 4 bits in NDRH group 3 is H FF4C and the address of the lower 4 bits group 2 is H FF4E Bits 3 to 0 of...

Page 446: ...standby mode It is not initialized in software standby mode Bits 7 and 6 Group 3 Compare Match Select 1 and 0 G3CMS1 G3CMS0 These bits select the compare match that triggers pulse output group 3 pins...

Page 447: ...nnel 3 Initial value 11 2 6 PPG Output Mode Register PMR Bit 7 6 5 4 3 2 1 0 G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV Initial value 1 1 1 1 0 0 0 0 R W R W R W R W R W R W R W R W R W PMR is an...

Page 448: ...it 4 G0INV Description 0 Inverted output for pulse output group 0 low level output at pin for a 1 in PODRL 1 Direct output for pulse output group 0 high level output at pin for a 1 in PODRL Initial va...

Page 449: ...pendent 1 and 0 output at compare match A or B in the selected TPU channel 11 2 7 Port 1 Data Direction Register P1DDR Bit 7 6 5 4 3 2 1 0 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initi...

Page 450: ...stop mode control When the MSTP11 bit in MSTPCR is set to 1 PPG operation stops at the end of the bus cycle and a transition is made to module stop mode Registers cannot be read or written to in modu...

Page 451: ...s the PPG operating conditions Output trigger signal Pulse output pin Internal data bus Normal output inverted output C PODR Q D NDER Q NDR Q D DDR Figure 11 2 PPG Output Operation Table 11 3 PPG Oper...

Page 452: ...to PODR and output when the specified compare match event occurs Figure 11 3 shows the timing of these operations for the case of normal output in groups 2 and 3 triggered by compare match A TCNT N N...

Page 453: ...R to make TGRA an output compare register with output disabled 2 Set the PPG output trigger period 3 Select the counter clock source with bits TPSC2 to TPSC0 in TCR Select the counter clear source wit...

Page 454: ...rrupt 2 Write H F8 in P1DDR and NDERH and set the G3CMS1 G3CMS0 G2CMS1 and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger Write outp...

Page 455: ...e non overlap margin in TGRA 3 Select the counter clock source with bits TPSC2 to TPSC0 in TCR Select the counter clear source with bits CCLR1 and CCLR0 4 Enable the TGIA interrupt in TIER The DTC or...

Page 456: ...match B Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt 2 Write H FF in P1DDR and NDERH and set the G3CMS1 G3CMS0 G2CMS1 and G2CMS0 bits in PCR to select compare match in the TPU channel s...

Page 457: ...es that are the inverse of the PODR contents can be output Figure 11 8 shows the outputs when G3INV and G2INV are cleared to 0 in addition to the settings of figure 11 7 TCNT value TCNT TGRB TGRA H 00...

Page 458: ...input capture as well as by compare match If TGRA functions as an input capture register in the TPU channel selected by PCR pulse output will be triggered by the input capture signal Figure 11 9 shows...

Page 459: ...anged only under conditions in which the output trigger event will not occur Note on Non Overlapping Output During non overlapping operation the transfer of NDR bit values to PODR bits takes place as...

Page 460: ...aving the TGIA interrupt handling routine write the next data in NDR or by having the TGIA interrupt activate the DTC or DMAC Note however that the next data must be written before the next compare ma...

Page 461: ...e cleared on compare match A or B or by an external reset signal Timer output control by a combination of two compare match signals The timer output signal in each channel is controlled by a combinati...

Page 462: ...tch A1 Compare match A0 Clear 1 CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Interrupt signals TMO0 TMRI0 Internal bus TCORA0 Comparator A0 Comparator B0 TCORB0 TCSR0 TCR0 TCORA1 Comparator A1 TCNT1 Comparator B...

Page 463: ...12 2 8 Bit Timer Registers Channel Name Abbreviation R W Initial value Address 1 0 Timer control register 0 TCR0 R W H 00 H FFB0 Timer control status register 0 TCSR0 R W 2 H 00 H FFB2 Time constant r...

Page 464: ...by clock clear bits CCLR1 and CCLR0 of TCR When a timer counter overflows from H FF to H 00 OVF in TCSR is set to 1 TCNT0 and TCNT1 are each initialized to H 00 by a reset and in hardware standby mode...

Page 465: ...t and in hardware standby mode 12 2 4 Time Control Registers 0 and 1 TCR0 TCR1 Bit 7 6 5 4 3 2 1 0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W...

Page 466: ...ernal clocks can be selected all divided from the system clock 8 64 and 8192 The falling edge of the selected internal clock triggers the count When use of an external clock is selected three types of...

Page 467: ...ialized to H 00 and TCSR1 to H 10 by a reset and in hardware standby mode Bit 7 Compare Match Flag B CMFB Status flag indicating whether the values of TCNT and TCORB match Bit 7 CMFB Description 0 Cle...

Page 468: ...h of TCOR and TCNT Bits OS3 and OS2 select the effect of compare match B on the output level bits OS1 and OS0 select the effect of compare match A on the output level and both of them can be controlle...

Page 469: ...When the MSTP12 bit in MSTPCR is set to 1 the 8 bit timer operation stops at the end of the bus cycle and a transition is made to module stop mode Registers cannot be read or written to in module sto...

Page 470: ...for Internal Clock Input External Clock Three incrementation methods can be selected by setting bits CKS2 to CKS0 in TCR at the rising edge the falling edge and both rising and falling edges Note that...

Page 471: ...ming TCNT N N 1 TCOR N Compare match signal CMF Figure 12 4 Timing of CMF Setting Timer Output Timing When compare match A or B occurs the timer output changes a specified by bits OS3 to OS0 in TCSR D...

Page 472: ...ar pulse width must be at least 1 5 states Figure 12 7 shows the timing of this operation Clear signal External reset input pin TCNT N H 00 N 1 Figure 12 7 Timing of External Reset 12 3 4 Timing of Ov...

Page 473: ...t counter TCNT0 and TCNT1 together is cleared when a 16 bit compare match event occurs The 16 bit counter TCNT0 and TCNT1 together is cleared even if counter clear by the TMRI0 pin has also been set T...

Page 474: ...tion Priority 0 CMIA0 Interrupt by CMFA Possible High CMIB0 Interrupt by CMFB Possible OVI0 Interrupt by OVF Not possible 1 CMIA1 Interrupt by CMFA Possible CMIB1 Interrupt by CMFB Possible OVI1 Inter...

Page 475: ...LR0 is set to 1 so that the timer counter is cleared when its value matches the constant in TCORA 2 In TCSR bits OS3 to OS0 are set to B 0110 causing the output to change to 1 at a TCORA compare match...

Page 476: ...between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle the clear takes priority so that the counter is cleared and the write is not performe...

Page 477: ...pulse is generated during the T2 state of a TCNT write cycle the write takes priority and the counter is not incremented Figure 12 11 shows this operation Address TCNT address Internal write signal T...

Page 478: ...ignal TCNT TCOR N M T1 T2 TCOR write cycle by CPU TCOR write data N N 1 Compare match signal Prohibited Figure 12 12 Contention between TCOR Write and Compare Match 12 6 4 Contention between Compare M...

Page 479: ...in case 3 in table 12 5 a TCNT clock pulse is generated on the assumption that the switchover is a falling edge This increments TCNT The erroneous incrementation can also happen when switching between...

Page 480: ...om low to stop and from stop to low 2 Includes switching from stop to high 3 Includes switching from high to stop 4 Generated on the assumption that the switchover is a falling edge TCNT is incremente...

Page 481: ...er interrupt is generated each time the counter overflows 13 1 1 Features WDT features are listed below Switchable between watchdog timer mode and interval timer mode WDTOVF output when in watchdog ti...

Page 482: ...ernal bus WDT Notes 1 The type of internal reset signal depends on a register setting Either power on reset or manual reset can be selected Manual reset is only supported in the H8S 2357 ZTAT 2 The WD...

Page 483: ...able 13 2 WDT Registers Address 1 Name Abbreviation R W Initial Value Write 2 Read Timer control status register TCSR R W 3 H 18 H FFBC H FFBC Timer counter TCNT R W H 00 H FFBC H FFBD Reset control s...

Page 484: ...ter Access 2 The WDTOVF pin function is not available in the F ZTAT version the H8S 2398 H8S 2394 H8S 2392 or H8S 2390 13 2 2 Timer Control Status Register TCSR Bit 7 6 5 4 3 2 1 0 OVF WT IT TME CKS2...

Page 485: ...section 13 2 3 Reset Control Status Register RSTCSR Bit 5 Timer Enable TME Selects whether TCNT runs or is halted Bit 5 TME Description 0 TCNT is initialized to H 00 and halted Initial value 1 TCNT c...

Page 486: ...ng 0 to WOVF 1 Setting condition Set when TCNT overflows changed from H FF to H 00 during watchdog timer operation Bit 6 Reset Enable RSTE Specifies whether or not a reset signal is generated in the H...

Page 487: ...A5 Write data 15 8 7 0 Figure 13 2 Format of Data Written to TCNT and TCSR Writing to RSTCSR RSTCSR must be written to by word transfer instruction to address H FFBE It cannot be written to with byte...

Page 488: ...a power on reset or a manual reset 2 depending on the setting of the RSTS bit in RSTCSR The internal reset signal is output for 518 states If a reset caused by a signal input to the RES pin occurs at...

Page 489: ...used to generate interrupt requests at regular intervals TCNT count H 00 Time H FF WT IT 0 TME 1 WOVI Overflow Overflow Overflow Overflow Legend WOVI Interval timer interrupt request generation WOVI...

Page 490: ...the timing in this case Note The WDTOVF pin function is not available in the F ZTAT version the H8S 2398 H8S 2394 H8S 2392 or H8S 2390 TCNT Note The WDTOVF pin function is not available in the F ZTAT...

Page 491: ...p the watchdog timer by clearing the TME bit to 0 before changing the value of bits CKS2 to CKS0 13 5 3 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watch...

Page 492: ...de The H8S 2357 Group is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer operation but TCNT and TSCR of the WDT are reset TCNT TCSR and RSTCR cannot be...

Page 493: ...processors Choice of 12 serial data transfer formats Data length 7 or 8 bits Stop bit length 1 or 2 bits Parity Even odd or none Multiprocessor bit 1 or 0 Receive error detection Parity overrun and fr...

Page 494: ...ssue requests independently The transmit data empty interrupt and receive data full interrupt can activate the DMA controller DMAC or data transfer controller DTC to execute data transfer Module stop...

Page 495: ...rial control register Serial status register Bit rate register Figure 14 1 Block Diagram of SCI 14 1 3 Pin Configuration Table 14 1 shows the serial pins for each SCI channel Table 14 1 SCI Pins Chann...

Page 496: ...FF7D Smart Card mode register 0 SCMR0 R W H F2 H FF7E 1 Serial mode register 1 SMR1 R W H 00 H FF80 Bit rate register 1 BRR1 R W H FF H FF81 Serial control register 1 SCR1 R W H 00 H FF82 Transmit dat...

Page 497: ...from RSR to RDR where it is stored and completes the receive operation After this RSR is receive enabled Since RSR and RDR function as a double buffer in this way enables continuous receive operation...

Page 498: ...l transfer format and select the baud rate generator clock source SMR can be read or written to by the CPU at all times SMR is initialized to H 00 by a reset and by putting the device in standby mode...

Page 499: ...the transmit character plus the parity bit is even In reception a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even 2 When odd parity is set...

Page 500: ...R is a register that performs enabling or disabling of SCI transfer operations serial clock output in asynchronous mode and interrupt requests and selection of the serial clock source SCR can be read...

Page 501: ...sion disabled 1 Initial value 1 Transmission enabled 2 Notes 1 The TDRE flag in SSR is fixed at 1 2 In this state serial transmission is started when transmit data is written to TDR and the TDRE flag...

Page 502: ...R are set to 1 and FER and ORER flag setting is enabled Bit 2 Transmit End Interrupt Enable TEIE Enables or disables transmit end interrupt TEI request generation when there is no valid transmit data...

Page 503: ...l Status Register SSR Bit 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT Initial value 1 0 0 0 0 1 0 0 R W R W R W R W R W R W R R R W Note Only 0 can be written to clear the flag SSR is an 8 bi...

Page 504: ...RDRF 1 2 Notes 1 The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0 2 The receive data prior to the overrun error is retained in RDR and the data recei...

Page 505: ...cannot be continued either Bit 2 Transmit End TEND Indicates that there is no valid data in TDR when the last bit of the transmit character is sent and transmission has been ended The TEND flag is rea...

Page 506: ...mode or module stop mode In the H8S 2398 H8S 2394 H8S 2392 and H8S 2390 however the value in BRR is initialized to H FF by a reset or in hardware standby mode but BRR retains its current state when th...

Page 507: ...00 0 15 1 73 19200 0 5 0 00 0 6 0 7 0 00 0 7 1 73 31250 0 3 0 00 0 4 1 70 0 4 0 00 38400 0 2 0 00 0 2 0 3 0 00 0 3 1 73 6 MHz 6 144 MHz 7 3728 MHz 8 MHz Bit Rate bit s n N Error n N Error n N Error n...

Page 508: ...0 15 0 00 0 15 1 73 0 19 2 34 0 19 0 00 31250 0 9 1 70 0 9 0 00 0 11 0 00 0 11 2 40 38400 0 7 0 00 0 7 1 73 0 9 2 34 0 9 0 00 14 MHz 14 7456 MHz 16 MHz 17 2032 MHz Bit Rate bit s n N Error n N Error n...

Page 509: ...34 0 15 0 00 0 15 1 73 Table 14 4 BRR Settings for Various Bit Rates Clocked Synchronous Mode Bit Rate 2 MHz 4 MHz 8 MHz 10 MHz 16 MHz 20 MHz bit s n N n N n N n N n N n N 110 3 70 250 2 124 2 249 3...

Page 510: ...1 B 106 1 Where B Bit rate bit s N BRR setting for baud rate generator 0 N 255 Operating frequency MHz n Baud rate generator input clock n 0 to 3 See the table below for the relation between n and th...

Page 511: ...ate for Each Frequency Asynchronous Mode MHz Maximum Bit Rate bit s n N 2 62500 0 0 2 097152 65536 0 0 2 4576 76800 0 0 3 93750 0 0 3 6864 115200 0 0 4 125000 0 0 4 9152 153600 0 0 5 156250 0 0 6 1875...

Page 512: ...8432 115200 8 2 0000 125000 9 8304 2 4576 153600 10 2 5000 156250 12 3 0000 187500 12 288 3 0720 192000 14 3 5000 218750 14 7456 3 6864 230400 16 4 0000 250000 17 2032 4 3008 268800 18 4 5000 281250...

Page 513: ...to H F2 by a reset or in hardware standby mode but SCMR retains its current state when the device enters software standby mode or module stop mode Bits 7 to 4 Reserved These bits cannot be modified a...

Page 514: ...n to in module stop mode For details see section 21 5 Module Stop Mode MSTPCR is initialized to H 3FFF by a reset and in hardware standby mode It is not initialized in software standby mode Bit 7 Modu...

Page 515: ...ation of these parameters determines the transfer format and character length Detection of framing parity and overrun errors and breaks during reception Choice of internal or external clock as SCI clo...

Page 516: ...0 1 0 Asynchronous 8 bit data Yes No 1 bit 1 1 0 1 mode multi processor format 7 bit data 2 bits 1 bit 2 bits 1 Clocked synchronous mode 8 bit data No None Table 14 9 SMR and SCR Settings and SCI Clo...

Page 517: ...ransmission line and when it goes to the space state low level recognizes a start bit and starts serial communication One serial communication character consists of a start bit low level followed by d...

Page 518: ...data STOP P S 8 bit data MPB STOP S 8 bit data MPB STOP STOP S 7 bit data STOP MPB S 7 bit data STOP MPB STOP S 7 bit data STOP STOP CHR 0 0 0 0 1 1 1 1 0 0 1 1 MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1...

Page 519: ...is in the middle of the transmit data as shown in figure 14 3 0 1 frame D0 D1 D2 D3 D4 D5 D6 D7 0 1 1 1 Figure 14 3 Relation between Output Clock and Transfer Data Phase Asynchronous Mode Data Transfe...

Page 520: ...l elapsed 1 Set the clock selection in SCR Be sure to clear bits RIE TIE TEIE and MPIE and bits TE and RE to 0 When the clock is selected in asynchronous mode it is output immediately after SCR settin...

Page 521: ...ntinuation procedure To continue serial transmission read 1 from the TDRE flag to confirm that writing is possible then write data to TDR and then clear the TDRE flag to 0 Checking and clearing of the...

Page 522: ...t is sent and then serial transmission of the next frame is started If the TDRE flag is set to 1 the TEND flag in SSR is set to 1 the stop bit is sent and then the mark state is entered in which 1 is...

Page 523: ...SSR to identify the error After performing the appropriate error processing ensure that the ORER PER and FER flags are all cleared to 0 Reception cannot be resumed if any of these flags are set to 1 I...

Page 524: ...ror processing Parity error processing Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error processing No Yes Overrun error processing ORER 1 FER 1 Break PER 1 Clear RE bit in S...

Page 525: ...ere are two stop bits only the first is checked c Status check The SCI checks whether the RDRF flag is 0 indicating that the receive data can be transferred from RSR to RDR If all the above checks are...

Page 526: ...Parity error PER When the received data differs from the parity even or odd set in SMR Receive data is transferred from RSR to RDR Figure 14 8 shows an example of the operation for reception in asynch...

Page 527: ...ving station skips the data until data with a 1 multiprocessor bit is sent When data with a 1 multiprocessor bit is received the receiving station compares that data with its own ID The station whose...

Page 528: ...n After the TE bit is set to 1 a frame of 1s is output and transmission is enabled SCI status check and transmit data write Read SSR and check that the TDRE flag is set to 1 then write transmit data t...

Page 529: ...3 The SCI checks the TDRE flag at the timing for sending the stop bit If the TDRE flag is cleared to 0 data is transferred from TDR to TSR the stop bit is sent and then serial transmission of the nex...

Page 530: ...ID reception cycle Set the MPIE bit in SCR to 1 SCI status check ID reception and comparison Read SSR and check that the RDRF flag is set to 1 then read the receive data in RDR and compare it with th...

Page 531: ...600H End Error processing Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error processing Overrun error processing ORER 1 FER 1 Break Clear RE bit in SCR to 0 5 Figure 14 12 Sam...

Page 532: ...gain RXI interrupt request is not generated and RDR retains its state ID1 a Data does not match station s ID MPIE RDR value 0 D0 D1 D7 1 1 0 D0 D1 D7 0 1 1 1 Data ID2 Start bit MPB Stop bit Start bit...

Page 533: ...Data confirmation is guaranteed at the rising edge of the serial clock In clocked serial communication one character consists of data output starting with the LSB and ending with the MSB After the MSB...

Page 534: ...ait Transfer start Start initialization Set data transfer format in SMR and SCMR No Yes Set value in BRR Clear TE and RE bits in SCR to 0 2 3 Set TE and RE bits in SCR to 1 and set RIE TIE TEIE and MP...

Page 535: ...1 SCI initialization The TxD pin is automatically designated as the transmit data output pin 2 SCI status check and transmit data write Read SSR and check that the TDRE flag is set to 1 then write tra...

Page 536: ...and ending with the MSB bit 7 3 The SCI checks the TDRE flag at the timing for sending the MSB bit 7 If the TDRE flag is cleared to 0 data is transferred from TDR to TSR and serial transmission of the...

Page 537: ...The RxD pin is automatically designated as the receive data input pin Receive error processing If a receive error occurs read the ORER flag in SSR and after performing the appropriate error processin...

Page 538: ...1 Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check 3 If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1 a rec...

Page 539: ...t data to TDR and clear the TDRE flag to 0 Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt Receive error processing If a receive error occurs read the ORER flag in SS...

Page 540: ...s generated When the TEND flag in SSR is set to 1 a TEI interrupt request is generated A TXI interrupt can activate the DMAC or DTC to perform data transfer The TDRE flag is cleared to 0 automatically...

Page 541: ...pt due to transmission end TEND Not possible Not possible 2 ERI Interrupt due to receive error ORER FER or PER Not possible Not possible RXI Interrupt due to receive data full state RDRF Possible Not...

Page 542: ...hat the TDRE flag is set to 1 before writing transmit data to TDR Operation when Multiple Receive Errors Occur Simultaneously If a number of receive errors occur at the same time the state of the stat...

Page 543: ...to 0 the transmitter is initialized regardless of the current transmission state the TxD pin becomes an I O port and 0 is output from the TxD pin Receive Error Flags and Transmit Operations Clocked Sy...

Page 544: ...l clock the transmit clock should not be input until at least 5 clock cycles after TDR is updated by the DMAC or DTC Misoperation may occur if the transmit clock is input within 4 clocks after TDR is...

Page 545: ...2357 Group are as follows Asynchronous mode Data length 8 bits Parity bit generation and checking Transmission of error signal parity error in receive mode Error signal detection and automatic data re...

Page 546: ...Serial status register Bit rate register Figure 15 1 Block Diagram of Smart Card Interface 15 1 3 Pin Configuration Table 15 1 shows the Smart Card interface pin configuration Table 15 1 Smart Card I...

Page 547: ...ter 0 RDR0 R H 00 H FF7D Smart Card mode register 0 SCMR0 R W H F2 H FF7E 1 Serial mode register 1 SMR1 R W H 00 H FF80 Bit rate register 1 BRR1 R W H FF H FF81 Serial control register 1 SCR1 R W H 00...

Page 548: ...a is stored in RDR LSB first 1 TDR contents are transmitted MSB first Receive data is stored in RDR MSB first Bit 2 Smart Card Data Invert SINV Specifies inversion of the data logic level This functio...

Page 549: ...nd in standby mode or module stop mode When 0 is written to ERS after reading ERS 1 1 Setting condition When the low level of the error signal is sampled Note Clearing the TE bit in SCR to 0 does not...

Page 550: ...ing of setting of the TEND flag that indicates transmission completion is advanced and clock output control mode addition is performed The contents of the clock output control mode addition are specif...

Page 551: ...ts 1 and 0 Clock Enable 1 and 0 CKE1 CKE0 These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin In Smart Card interface mode in addition to the normal...

Page 552: ...atic diagram of Smart Card interface related pin connections In communication with an IC card since both transmission and reception are carried out on a single data transmission line the TxD pin and R...

Page 553: ...ith a pull up resistor 2 The transmitting station starts transfer of one frame of data The data frame starts with a start bit Ds low level followed by 8 data bits D0 to D7 and a parity bit Dp 3 With t...

Page 554: ...0 select the clock source of the on chip baud rate generator See section 15 3 5 Clock BRR Setting BRR is used to set the bit rate See section 15 3 5 Clock for the method of calculating the value to be...

Page 555: ...onding to state Z since even parity is stipulated for the Smart Card With the H8S 2357 Group inversion specified by the SINV bit applies only to the data bits D7 to D0 For parity bit inversion the O E...

Page 556: ...her hand is shown below N is an integer 0 N 255 and the smaller error is specified N 1488 22n 1 B 106 1 Table 15 6 Examples of BRR Settings for Bit Rate B bit s When n 0 MHz 7 1424 10 00 10 7136 13 00...

Page 557: ...4 shows a flowchart for transmitting and figure 15 5 shows the relation between a transmit operation and the internal registers 1 Perform Smart Card interface mode initialization as described above i...

Page 558: ...on No Yes Clear TE bit to 0 Start transmission Start No No No Yes Yes Yes Yes No End Write data to TDR and clear TDRE flag in SSR to 0 Error processing Error processing TEND 1 All data transmitted TEN...

Page 559: ...n completed In case of normal transmission TEND flag is set In case of transmit error ERS flag is set Steps 2 and 3 above are repeated until the TEND flag is set I O signal line output Data 1 Data 1 F...

Page 560: ...RE bit to 0 Initialization Read RDR and clear RDRF flag in SSR to 0 Clear RE bit to 0 Start reception Start Error processing No No No Yes Yes ORER 0 and PER 0 RDRF 1 All data received Yes Figure 15 7...

Page 561: ...xing Clock Output Level Interrupt Operation There are three interrupt sources in Smart Card interface mode transmit data empty interrupt TXI requests transfer error interrupt ERI requests and receive...

Page 562: ...by the DMAC or DTC If an error occurs an error flag is set but the RDRF flag is not Consequently the DMAC or DTC is not activated but instead an ERI interrupt request is sent to the CPU Therefore the...

Page 563: ...ng points should be noted when using the SCI as a Smart Card interface Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode In Smart Card Interface mode the SCI operates on a...

Page 564: ...checked the PER bit in SSR is not set to 1 4 If no error is found when the received parity bit is checked the receive operation is judged to have been completed normally and the RDRF flag in SSR is au...

Page 565: ...he TEND bit in SSR is set to 1 If the TIE bit in SCR is enabled at this time a TXI interrupt request is generated If data transfer by the DMAC or DTC by means of the TXI source is enabled the next dat...

Page 566: ...Rev 6 00 Oct 28 2004 page 538 of 1016 REJ09B0138 0600H...

Page 567: ...Minimum conversion time 6 7 s per channel at 20 MHz operation Choice of single mode or scan mode Single mode Single channel A D conversion Scan mode Continuous A D conversion on 1 to 4 channels Four...

Page 568: ...trigger from TPU Successive approximations register Multiplexer ADCR ADCSR ADDRA ADDRB ADDRC ADDRD A D control register A D control status register A D data register A A D data register B A D data reg...

Page 569: ...gger input pin ADTRG Input External trigger input for starting A D conversion 16 1 4 Register Configuration Table 16 2 summarizes the registers of the A D converter Table 16 2 A D Converter Registers...

Page 570: ...og input channels and ADDR registers is shown in table 16 3 ADDR can always be read by the CPU The upper byte can be read directly but for the lower byte data transfer is performed via a temporary reg...

Page 571: ...on The ADST bit can be set to 1 by software a timer conversion start trigger or the A D external trigger input pin ADTRG Bit 5 ADST Description 0 A D conversion stopped Initial value 1 Single mode A D...

Page 572: ...isables external triggering of A D conversion operations ADCR is initialized to H 3F by a reset and in standby mode or module stop mode Bits 7 and 6 Timer Trigger Select 1 and 0 TRGS1 TRGS0 Select ena...

Page 573: ...When the MSTP9 bit in MSTPCR is set to 1 A D converter operation stops at the end of the bus cycle and a transition is made to module stop mode Registers cannot be read or written to in module stop m...

Page 574: ...er byte but if only the lower byte is read incorrect data may be obtained Figure 16 2 shows the data flow for ADDR access Bus master H AA ADDRnH H AA ADDRnL H 40 Lower byte read ADDRnH H AA ADDRnL H 4...

Page 575: ...and A D conversion is started ADST 1 2 When A D conversion is completed the result is transferred to ADDRB At the same time the ADF flag is set to 1 the ADST bit is cleared to 0 and the A D converter...

Page 576: ...input channels AN0 to AN2 are selected CH1 1 CH0 0 and A D conversion is started ADST 1 2 When A D conversion of the first channel AN0 is completed the result is transferred to ADDRA Next conversion o...

Page 577: ...time therefore varies within the ranges indicated in table 16 4 In scan mode the values given in table 16 4 apply to the first conversion time In the second and subsequent conversions the conversion...

Page 578: ...gger signal ADST A D conversion Figure 16 6 External Trigger Input Timing 16 5 Interrupts The A D converter generates an A D conversion end interrupt ADI at the end of A D conversion ADI interrupt req...

Page 579: ...cuitry due to inductance adversely affecting A D conversion values Also digital circuitry must be isolated from the analog input signals AN0 to AN7 analog reference power supply Vref and analog power...

Page 580: ...tage value B 0000000000 H 000 to B 0000000001 H 001 see figure 16 9 Full scale error The deviation of the analog input voltage value from the ideal A D conversion characteristic when the digital outpu...

Page 581: ...A D conversion characteristic Full scale error Figure 16 9 A D Conversion Precision Definitions 2 Permissible Signal Source Impedance H8S 2357 Group analog input is designed so that conversion precisi...

Page 582: ...peed analog signal a low impedance buffer should be inserted Influences on Absolute Precision Adding capacitance results in coupling with GND and therefore noise in GND may adversely affect absolute p...

Page 583: ...ge of 0 V to Vref D A output hold function in software standby mode Module stop mode can be set As the initial setting D A converter operation is halted Register access is enabled by exiting module st...

Page 584: ...pin 0 DA0 Output Channel 0 analog output Analog output pin 1 DA1 Output Channel 1 analog output Reference voltage pin Vref Input Analog reference voltage 17 1 4 Register Configuration Table 17 2 summa...

Page 585: ...ol Register DACR Bit 7 6 5 4 3 2 1 0 DAOE1 DAOE0 DAE Initial value 0 0 0 1 1 1 1 1 R W R W R W R W DACR is an 8 bit readable writable register that controls the operation of the D A converter DACR is...

Page 586: ...is the same as during D A conversion When it is necessary to reduce the analog power current in software standby mode clear both the DAOE0 and DAOE1 bits to 0 to disable D A output Bits 4 to 0 Reserv...

Page 587: ...ersion is started and the DA0 pin becomes an output pin The conversion result is output after the conversion time has elapsed The output value is expressed by the following formula DADR contents Vref...

Page 588: ...Rev 6 00 Oct 28 2004 page 560 of 1016 REJ09B0138 0600H...

Page 589: ...a is possible The on chip RAM can be enabled or disabled by means of the RAM enable bit RAME in the system control register SYSCR 18 1 1 Block Diagram Figure 18 1 shows a block diagram of the 8 kbytes...

Page 590: ...p RAM is enabled Initial value 18 3 Operation When the RAME bit is set to 1 accesses to addresses H FFDC00 to H FFFBFF are directed to the on chip RAM When the RAME bit is cleared to 0 the off chip ad...

Page 591: ...programmed on board as well as with a PROM programmer The PROM version of the H8S 2357 Group can be programmed with a PROM programmer by setting PROM mode 19 1 1 Block Diagram Figure 19 1 shows a bloc...

Page 592: ...latches are canceled by a power on reset but are retained after a manual reset Note Manual reset is only supported in the H8S 2357 ZTAT 19 2 2 Bus Control Register L BCRL Bit 7 6 5 4 3 2 1 0 BRLE BREQ...

Page 593: ...tes 1 1 Enabled 64 kbytes Mode 8 1 0 0 0 Mode 9 1 Mode 10 Boot mode advanced 1 0 0 Enabled 128 kbytes 2 expanded mode with on chip ROM enabled 3 1 Enabled 64 kbytes Mode 11 Boot mode advanced 1 0 Enab...

Page 594: ...Operating Mode 2 In the H8S 2398 F ZTAT modes 2 and 3 indicate boot mode For details on boot mode of H8S 2398 F ZTAT refer to table 19 35 in section 19 17 On Board Programming Modes In addition for de...

Page 595: ...PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PB0 NMI PB2 PB3 PB4 PB5 PB6 PB7 PA0 PF2 PB1 PF1 VCC AVCC Vref PA1 PA2 VSS AVSS STBY MD0 MD1 MD2 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22...

Page 596: ...9 5 Socket Adapter Microcontroller Package Socket Adapter H8S 2357 120 pin TQFP TFP 120 HS2655ESNS1H 128 pin QFP FP 128B HS2655ESHS1H On chip PROM Addresses in MCU mode Addresses in PROM mode H 000000...

Page 597: ...L L L VPP VCC High impedance Address input L H H H L L H H H Legend L Low voltage level H High voltage level VPP VPP voltage level VCC VCC voltage level Programming and verification should be carried...

Page 598: ...dresses Figure 19 4 shows the basic high speed programming flowchart Tables 19 7 and 19 8 list the electrical characteristics of the chip during programming Figure 19 5 shows a timing chart Start Set...

Page 599: ...ROM Mode Conditions VCC 6 0 V 0 25 V VPP 12 5 V 0 3 V Ta 25 C 5 C Item Symbol Min Typ Max Unit Test Conditions Address setup time tAS 2 s Figure 19 5 1 OE setup time tOES 2 s Data setup time tDS 2 s A...

Page 600: ...s of the specified values can permanently destroy the MCU Be particularly careful about the PROM programmer s overshoot characteristics Before programming check that the MCU is correctly mounted in th...

Page 601: ...19 6 shows the recommended screening procedure Mount Program chip and verify data Bake chip for 24 to 48 hours at 125 C to 150 C with power off Read and check program Figure 19 6 Recommended Screening...

Page 602: ...lent to 300 s typ per byte and the erase time is 100 ms typ per block Reprogramming capability The flash memory can be reprogrammed up to 100 times On board programming modes There are two modes in wh...

Page 603: ...e FLMCR2 Internal address bus Internal data bus 16 bits FWE pin Mode pins EBR1 EBR2 FLMCR1 SYSCR2 RAMER Legend SYSCR2 System control register 2 FLMCR1 Flash memory control register 1 FLMCR2 Flash memo...

Page 604: ...t not programmed or erased Flash memory can be programmed and erased in boot mode user program mode and programmer mode Boot mode On board programming mode User program mode User mode with on chip ROM...

Page 605: ...cation program beforehand in the host 2 Programming control program transfer When boot mode is entered the boot program in the H8S 2357 chip originally incorporated in the chip is started and the prog...

Page 606: ...beforehand 3 The programming erase control program should be prepared in the host or in the flash memory 2 Programming erase control program transfer When the FWE pin is driven high user software conf...

Page 607: ...n data written in RAM Figure 19 11 Reading Overlap Data in User Mode and User Program Mode Writing Overlap Data in User Program Mode When overlap RAM data is confirmed the RAMS bit is cleared RAM over...

Page 608: ...rogram program verify Program program verify Erase erase verify Note To be provided by the user in accordance with the recommended algorithm Block Configuration The flash memory is divided into two 32...

Page 609: ...er Name Abbreviation R W Initial Value Address 1 Flash memory control register 1 FLMCR1 6 R W 3 H 00 4 H FFC8 2 Flash memory control register 2 FLMCR2 6 R W 3 H 00 5 H FFC9 2 Erase block register 1 EB...

Page 610: ...low level is input When on chip flash memory is disabled a read will return H 00 and writes are invalid Writes to the SWE bit in FLMCR1 are enabled only when FWE 1 writes to the EV and PV bits only w...

Page 611: ...same time Bit 2 PV Description 0 Program verify mode cleared Initial value 1 Transition to program verify mode Setting condition When FWE 1 and SWE 1 Bit 1 Erase E Selects erase mode transition or cl...

Page 612: ...emory goes to the error protection state Bit 7 FLER Description 0 Flash memory is operating normally Flash memory program erase protection error protection is disabled Clearing condition Reset or hard...

Page 613: ...and software standby mode when a low level is input to the FWE pin and when a high level is input to the FWE pin and the SWE bit in FLMCR1 is not set When a bit in EBR1 or EBR2 is set the correspondi...

Page 614: ...the flash memory control register contents are retained Bit 3 FLSHE Description 0 Flash control registers deselected in area H FFFFC8 to H FFFFCB Initial value 1 Flash control registers selected in ar...

Page 615: ...ial value 1 Emulation selected Program erase protection of all flash memory blocks is enabled Bits 1 and 0 Flash Memory Area Selection RAM1 RAM0 These bits are used together with bit 2 to select the f...

Page 616: ...the flash memory programming control program must be prepared in the host beforehand The channel 1 SCI to be used is set to asynchronous mode When a reset start is executed after the H8S 2357 MCU s pi...

Page 617: ...ndication H 00 and transmits one H 55 data byte After receiving H 55 MCU transmits one H AA data byte to host Host transmits number of programming control program bytes N upper byte followed by lower...

Page 618: ...on the host s transmission bit rate and the MCU s system clock frequency there will be a discrepancy between the bit rates of the host and the MCU To ensure correct SCI operation the host s transfer b...

Page 619: ...n user program mode is accidentally erased Interrupts cannot be used while the flash memory is being programmed or erased The RxD1 and TxD1 pins should be pulled up on the board Before branching to th...

Page 620: ...s 3 See Appendix D Pin States 19 8 2 User Program Mode When set to user program mode the chip can program and erase its flash memory by executing a user program erase control program Therefore on boar...

Page 621: ...er program and the program erase control program if necessary beforehand Notes Do not apply a constant high level to the FWE pin Apply a high level to the FWE pin only when the flash memory is program...

Page 622: ...d in the program data area and reprogram data area and the 32 byte data in the reprogram data area written consecutively to the write addresses The lower 8 bits of the first address written to must be...

Page 623: ...ear SWE bit in FLMCR1 n N n n 1 Notes 1 Data transfer is performed by byte transfer The lower 8 bits of the first address written to must be H 00 H 20 H 40 H 60 H 80 H A0 H C0 or H E0 A 32 byte data t...

Page 624: ...e starting the erase procedure 19 9 4 Erase Verify Mode In erase verify mode data is read after memory has been erased to check whether it has been correctly erased After the elapse of the erase time...

Page 625: ...V bit in FLMCR1 Clear SWE bit in FLMCR1 Disable WDT Halt erase 1 Verify data all 1 Last address of block End of erasing of all erase blocks Erase failure Clear SWE bit in FLMCR1 n N NG NG NG NG OK OK...

Page 626: ...Table 19 16 Hardware Protection Functions Item Description Program Erase FWE pin protection When a low level is input to the FWE pin FLMCR1 FLMCR2 excluding the FLER bit EBR1 and EBR2 are initialized...

Page 627: ...s detected when MCU runaway occurs during flash memory programming erasing or operation is not performed in accordance with the program erase algorithm and the program erase operation is aborted Abort...

Page 628: ...ror protection mode software standby Software standby mode FLMCR1 FLMCR2 except FLER bit EBR1 EBR2 initialization state FLMCR1 FLMCR2 EBR1 EBR2 initialization state Software standby mode release RD Me...

Page 629: ...fter the RAMER setting has been made accesses can be made from the flash memory area or the RAM area overlapping flash memory Emulation can be performed in user mode and user program mode Figure 19 22...

Page 630: ...apping RAM 3 After the program data has been confirmed the RAMS bit is cleared releasing RAM overlap 4 The data written in the overlapping RAM is written into the flash memory space EB1 Notes 1 When t...

Page 631: ...ormal boot mode sequence For these reasons in on board programming mode alone there are conditions for disabling interrupt as an exception to the general rule However this provision does not guarantee...

Page 632: ...Pin Settings Pin Names Settings External Circuit Connection Mode pins MD2 MD1 MD0 Low level input Mode setting pins P66 P65 P64 High level input to P66 low level input to P65 and P64 FWE pin High leve...

Page 633: ...erasing Status Read Mode Status polling is used for auto programming and auto erasing and normal termination can be confirmed by reading the I O6 signal In status read mode error information is output...

Page 634: ...e cycles n 19 13 4 Memory Read Mode After the end of an auto program auto erase or status read operation the command wait state is entered To read memory contents a transition must be made to memory r...

Page 635: ...gure 19 25 Memory Read Mode Timing Waveforms after Command Write Table 19 22 AC Characteristics when Entering Another Mode from Memory Read Mode Conditions VCC 5 0 V 10 VSS 0 V Ta 25 C 5 C Item Symbol...

Page 636: ...Mode from Memory Read Mode Table 19 23 AC Characteristics in Memory Read Mode Conditions VCC 5 0 V 10 VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit Access time tacc 20 s CE output delay time tce 150 ns...

Page 637: ...m Mode Conditions VCC 5 0 V 10 VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit Command write cycle tnxtc 20 s CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 5...

Page 638: ...resses The lower 8 bits of the transfer address must be H 00 or H 80 If a value other than an effective address is input processing will switch to a memory write operation but a write error will be fl...

Page 639: ...e time tr 30 ns WE fall time tf 30 ns Erase setup time tens 100 ns Erase end setup time tenh 100 ns CE FWE Address Data I O6 I O7 OE WE tests tnxtc tnxtc tces tceh tdh CLin DLin twep tens I O0 to I O5...

Page 640: ...r other than status read mode is performed Table 19 26 AC Characteristics in Status Read Mode Conditions VCC 5 0 V 10 VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit Command write cycle tnxtc 20 s CE hol...

Page 641: ...7 status polling flag indicates the operating status in auto program or auto erase mode The I O6 status polling flag indicates a normal or abnormal end in auto program or auto erase mode Table 19 28 S...

Page 642: ...ROM mode are summarized below Use the specified voltages and timing for programming and erasing Applied voltages in excess of the rating can permanently damage the device Use a PROM programmer that su...

Page 643: ...tion in flash memory Clear the SWE bit before executing a program or reading data in flash memory When the SWE bit is set data in flash memory can be rewritten but flash memory should only be accessed...

Page 644: ...y are disabled Always fix the level by pulling down or pulling up the mode pins MD2 to MD0 until powering off except for mode switching See section 22 7 6 Flash Memory Characteristics Notes VCC FWE tO...

Page 645: ...rify are disabled Always fix the level by pulling down or pulling up the mode pins MD2 to MD0 up to powering off except for mode switching See section 22 7 6 Flash Memory Characteristics Notes VCC FWE...

Page 646: ...re do not use these pins as output signals during this switching period When making a transition from the boot mode to another mode the mode programming setup time tMDS min 200 ns relative to the RES...

Page 647: ...typ Reprogramming capability Depending on the product the maximum number of times the flash memory can be reprogrammed is either 100 or 1 000 Reprogrammable up to 100 times HD64F2398TE HD64F2398F Rep...

Page 648: ...ating mode EBR1 Internal address bus Internal data bus 16 bits Mode pins EBR2 SYSCR2 FLMCR2 FLMCR1 RAMER Legend FLMCR1 Flash memory control register 1 FLMCR2 Flash memory control register 2 EBR1 Erase...

Page 649: ...ad but not programmed or erased Flash memory can be programmed and erased in boot mode user program mode and PROM mode Boot mode On board programming mode User program mode User mode on chip ROM enabl...

Page 650: ...forehand in the host 2 Programming control program transfer When boot mode is entered the boot program in the chip originally incorporated in the chip is started and the programming control program in...

Page 651: ...programming erase control program should be prepared in the host or in the flash memory 2 Programming erase control program transfer Executes the transfer program in the flash memory and transfers the...

Page 652: ...n data written in RAM Figure 19 40 Reading Overlap RAM Data in User Mode and User Program Mode Writing Overlap RAM Data in User Program Mode When overlap RAM data is confirmed the RAMS bit is cleared...

Page 653: ...g control program Program program verify Erase erase verify program program verify emulation Note To be provided by the user in accordance with the recommended algorithm 19 15 7 Block Configuration Pr...

Page 654: ...YSCR2 except RAMER Table 19 32 Flash Memory Registers Register Name Abbreviation R W Initial Value Address 1 Flash memory control register 1 FLMCR1 5 R W 3 H 80 H FFC8 2 Flash memory control register...

Page 655: ...to the E bit is enabled only when SWE 1 and ESU 1 and writing to the P bit is enabled only when SWE 1 and PSU 1 Bit 7 Flash Write Enable Bit FWE Sets hardware protection against flash memory programm...

Page 656: ...at the same time Bit 2 PV Description 0 Program verify mode cleared Initial value 1 Transition to program verify mode Setting condition When SWE 1 Bit 1 Erase E Selects erase mode transition or cleari...

Page 657: ...mode 1 An error has occurred during flash memory programming erasing Flash memory program erase protection error protection is enabled Setting condition See section 19 19 3 Error Protection Bits 6 to...

Page 658: ...configuration is shown in table 19 33 Table 19 33 Flash Memory Erase Blocks Block Size Address EB0 4 kbytes H 000000 to H 000FFF EB1 4 kbytes H 001000 to H 001FFF EB2 4 kbytes H 002000 to H 002FFF EB3...

Page 659: ...o be overlapped with part of RAM when emulating real time flash memory programming RAMER is initialized to H 00 by a reset and in hardware standby mode It is not initialized in software standby mode R...

Page 660: ...kbytes 1 1 1 1 Don t care 19 17 On Board Programming Modes When pins are set to on board programming mode program erase verify operations can be performed on the on chip flash memory There are two on...

Page 661: ...ng control program received via the SCI is written into the programming control program area in on chip RAM After the transfer is completed control branches to the start address of the programming con...

Page 662: ...ndication H 00 and transmits one H 55 data byte After receiving H 55 chip transmits one H AA data byte to host Host transmits number of programming control program bytes N upper byte followed by lower...

Page 663: ...t and repeat the above operations Depending on the host s transmission bit rate and the chip s system clock frequency there will be a discrepancy between the bit rates of the host and the chip To ensu...

Page 664: ...ry if all data is not 1 all flash memory blocks are erased Boot mode is for use when user program mode is unavailable such as the first time on board programming is performed or if the program activat...

Page 665: ...ogram in part of the program area if necessary To select user program mode select a mode that enables the on chip flash memory mode 6 or 7 In this mode on chip supporting modules other than flash memo...

Page 666: ...m data area and the 128 byte data in the reprogram data area is written consecutively to the write addresses The lower 8 bits of the first address written to must be H 00 or H 80 128 consecutive byte...

Page 667: ...area 128 bytes Store 128 byte program data in program data area and reprogram data area Number of Writes n 1 2 3 4 5 6 7 8 9 10 11 12 13 998 999 1000 Write Time z s z1 z1 z1 z1 z1 z1 z2 z2 z2 z2 z2 z...

Page 668: ...rocedure 19 18 4 Erase Verify Mode In erase verify mode data is read after memory has been erased to check whether it has been correctly erased After the elapse of the erase time erase mode is exited...

Page 669: ...ar EV bit in FLMCR1 Clear SWE bit in FLMCR1 Disable WDT Halt erase 1 Verify data all 1 Last address of block End of erasing of all erase blocks Erase failure Clear SWE bit in FLMCR1 n N NG NG NG NG OK...

Page 670: ...CR1 FLMCR2 and erase block registers 1 and 2 EBR1 EBR2 are reset See table 19 37 Table 19 37 Hardware Protection Functions Item Description Program Erase Reset standby protection In a reset including...

Page 671: ...ee table 19 38 Table 19 38 Software Protection Functions Item Description Program Erase SWE bit protection Clearing the SWE bit to 0 in FLMCR1 sets the program erase protected state for all blocks Exe...

Page 672: ...ing including a vector read or instruction fetch Immediately after exception handling excluding a reset during programming erasing When a SLEEP instruction including software standby is executed durin...

Page 673: ...ter the RAMER setting has been made accesses can be made from the flash memory area or the RAM area overlapping flash memory Emulation can be performed in user mode and user program mode Figure 19 51...

Page 674: ...ramming is performed using the overlapping RAM 3 After the program data has been confirmed the RAMS bit is cleared releasing RAM overlap 4 The data written in the overlapping RAM is written into the f...

Page 675: ...ng control program has completed programming 2 The vector may not be read correctly in this case for the following two reasons If flash memory is read while being programmed or erased while the P or E...

Page 676: ...pter is connected to the chip as shown in figure 19 54 Figure 19 53 shows the on chip ROM memory map and figure 19 54 show the socket adapter pin assignments H 00000000 MCU mode address Programmer mod...

Page 677: ...8 9 11 12 13 14 15 16 17 18 20 21 22 23 24 25 26 49 50 51 52 54 55 56 57 76 77 75 80 81 85 86 RES XTAL EXTAL NC OPEN 1 30 33 52 55 74 75 76 81 93 94 6 15 24 31 32 38 47 59 66 79 103 104 113 114 115 5...

Page 678: ...ut if an error occurs Table 19 40 Settings for Each Operating Mode in Programmer Mode Pin Names Mode CE OE WE I O7 to I O0 A18 to A0 Read L L H Data output Ain Output disable L H H Hi Z Command write...

Page 679: ...ed consecutive reads can be performed After power on memory read mode is entered Table 19 42 AC Characteristics in Memory Read Mode Conditions VCC 5 0 V 10 VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit...

Page 680: ...rise time tr 30 ns WE fall time tf 30 ns CE A18 to A0 I O7 to I O0 OE WE Other mode command write tceh tds tdh tf tr tnxtc Note Do not enable WE and OE at the same time tces twep Memory read mode Add...

Page 681: ...fer address must be held low If an invalid address is input memory programming will be started but a programming error will occur Memory address transfer is executed in the second cycle figure 19 59 D...

Page 682: ...width twep 70 ns Status polling start time twsts 1 ms Status polling access time tspa 150 ns Address setup time tas 0 ns Address hold time tah 60 ns Memory write time twrite 1 3000 ms WE rise time tr...

Page 683: ...ading is possible by enabling CE and OE AC Characteristics Table 19 46 AC Characteristics in Auto Erase Mode Conditions VCC 5 0 V 10 VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit Command write cycle tn...

Page 684: ...Mode Conditions VCC 5 0 V 10 VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit Command write cycle tnxtc 20 s CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50...

Page 685: ...normal or abnormal end in auto program or auto erase mode Table 19 49 Status Polling Output Truth Table Pin Names Internal Operation in Progress Abnormal End Normal End I O7 0 1 0 1 I O6 0 0 1 1 I O0...

Page 686: ...and place the flash memory in the hardware protection state The power on and power off timing requirements should also be satisfied in the event of a power failure and subsequent recovery Use the reco...

Page 687: ...ming unit block erased Before programming check that the chip is correctly mounted in the PROM programmer Overcurrent damage to the device can result if the index marks on the PROM programmer socket s...

Page 688: ...Rev 6 00 Oct 28 2004 page 660 of 1016 REJ09B0138 0600H...

Page 689: ...1 shows a block diagram of the clock pulse generator EXTAL XTAL Duty adjustment circuit Oscillator Medium speed divider System clock to pin Internal clock to supporting modules Bus master clock to CPU...

Page 690: ...Standby Mode 0 output initial value output Fixed high High impedance 1 Fixed high Fixed high Fixed high High impedance Bit 6 Reserved This bit can be read or written to but only 0 should be written Bi...

Page 691: ...XTAL Rd CL2 CL1 CL1 CL2 10 to 22 pF Figure 20 2 Connection of Crystal Resonator Example Table 20 2 Damping Resistance Value Frequency MHz 2 4 8 10 12 16 20 Rd 1k 500 200 0 0 0 0 Crystal Resonator Fig...

Page 692: ...L1 H8S 2357 Group XTAL EXTAL Avoid Figure 20 4 Example of Incorrect Board Design 20 3 2 External Clock Input Circuit Configuration An external clock signal can be input as shown in the examples in fig...

Page 693: ...ns 5 MHz Clock high pulse width tCH 0 4 0 6 0 4 0 6 tcyc 5 MHz level 80 80 ns 5 MHz tEXH tEXL tEXr tEXf VCC 0 5 EXTAL Figure 20 6 External Clock Input Timing 20 4 Duty Adjustment Circuit When the osc...

Page 694: ...Rev 6 00 Oct 28 2004 page 666 of 1016 REJ09B0138 0600H...

Page 695: ...the conditions for transition to the various modes the status of the CPU on chip supporting modules etc and the method of clearing each mode Table 21 1 Operating Modes Operating Transition Clearing CP...

Page 696: ...ble 21 2 summarizes these registers Table 21 2 Power Down Mode Registers Name Abbreviation R W Initial Value Address Standby control register SBYCR R W H 08 H FF38 System clock control register SCKCR...

Page 697: ...o sleep mode after execution of SLEEP instruction Initial value 1 Transition to software standby mode after execution of SLEEP instruction Bits 6 to 4 Standby Timer Select 2 to 0 STS2 to STS0 These bi...

Page 698: ...W R W R W Note R W in the H8S 2390 H8S 2392 H8S 2394 and H8S 2398 SCKCR is an 8 bit readable writable register that performs clock output control and medium speed mode control SCKCR is initialized to...

Page 699: ...TPCR MSTPCRH MSTPCRL Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W MSTPCR is a 16 bit read...

Page 700: ...stored If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1 a transition is made to software standby mode When software standby mode is cleared by an external interrupt medium spe...

Page 701: ...After reset clearance all modules other than DMAC and DTC are in module stop mode When an on chip supporting module is in module stop mode read write access to its registers is disabled Do not make a...

Page 702: ...ted For details refer to section 7 DMA Controller and section 8 Data Transfer Controller On Chip Supporting Module Interrupt Relevant interrupt operations cannot be performed in module stop mode Conse...

Page 703: ...ime set in bits STS2 to STS0 in SYSCR stable clocks are supplied to the entire H8S 2357 Group chip software standby mode is cleared and interrupt exception handling is started When clearing software s...

Page 704: ...1 3 1 6 2 0 2 7 4 0 8 0 s Recommended time setting Using an External Clock Any value can be set Normally use of the minimum time is recommended Note The 16 state standby time cannot be used in the F Z...

Page 705: ...for the output current when a high level signal is output Current Dissipation during Oscillation Stabilization Wait Period Current dissipation increases during the oscillation stabilization wait peri...

Page 706: ...the STBY pin and the RES pin When the STBY pin is driven high while the RES pin is low the reset state is set and clock oscillation is started Ensure that the RES pin is held low until the clock osci...

Page 707: ...goes high clock output is enabled when the PSTOP bit is cleared to 0 When DDR for the corresponding port is cleared to 0 clock output is disabled and input port mode is set Table 21 5 shows the state...

Page 708: ...Rev 6 00 Oct 28 2004 page 680 of 1016 REJ09B0138 0600H...

Page 709: ...VCC 0 3 V Input voltage port 4 Vin 0 3 to AVCC 0 3 V Reference voltage Vref 0 3 to AVCC 0 3 V Analog power supply voltage AVCC 0 3 to 7 0 V Analog input voltage VAN 0 3 to AVCC 0 3 V Operating tempera...

Page 710: ...0 7 VCC 0 3 V Ports 1 3 5 B to G P60 to P63 PA0 to PA3 2 0 VCC 0 3 V Port 4 2 0 AVCC 0 3 V Input low voltage RES STBY MD2 to MD0 VIL 0 3 0 5 V NMI EXTAL Ports 1 3 to 5 B to G P60 to P63 PA0 to PA3 0...

Page 711: ...C 4 5 V VIH min VCC 0 9 and VIL max 0 3 V 4 ICC depends on VCC and f as follows ICC max 3 0 mA 0 60 mA MHz V VCC f normal mode ICC max 3 0 mA 0 48 mA MHz V VCC f sleep mode Table 22 3 Permissible Outp...

Page 712: ...600 The chip Ports 1 A to C LED Figure 22 2 LED Drive Circuit Example 22 1 3 AC Characteristics Figure 22 3 show the test conditions for the AC characteristics C LSI output pin RH RL C 90 pF Ports 1 A...

Page 713: ...dition Test Item Symbol Min Max Unit Conditions Clock cycle time t cyc 50 100 ns Figure 22 4 Clock high pulse width t CH 20 ns Clock low pulse width t CL 20 ns Clock rise time t Cr 5 ns Clock fall tim...

Page 714: ...4 5 V to AVCC VSS AVSS 0 V 10 to 20 MHz Ta 20 to 75 C regular specifications Ta 40 to 85 C wide range specifications Condition Test Item Symbol Min Max Unit Conditions RES setup time t RESS 200 ns Fig...

Page 715: ...28 2004 page 687 of 1016 REJ09B0138 0600H tRESS tRESW tRESS RES Figure 22 6 Reset Input Timing tIRQS tNMIS tNMIH IRQ Edge input NMI tIRQS tIRQH IRQ IRQ Level input tNMIW tIRQW Figure 22 7 Interrupt I...

Page 716: ...delay time 2 tCSD2 20 ns CS delay time 3 tCSD3 25 ns AS delay time tASD 20 ns RD delay time 1 tRSD1 20 ns RD delay time 2 tRSD2 20 ns CAS delay time tCASD 20 ns Read data setup time tRDS 15 ns Read d...

Page 717: ...time tWTS 30 ns Figure 22 10 WAIT hold time tWTH 5 ns BREQ setup time tBRQS 30 ns Figure 22 16 BACK delay time tBACD 15 ns Bus floating time tBZD 50 ns BREQO delay time tBRQOD 30 ns Figure 22 17 tRSD2...

Page 718: ...38 0600H tRSD2 T2 AS A23 to A0 tASD RD read T3 tAS tAH tASD tACC4 tRSD1 tACC5 tAS tRDS tRDH tWRD1 tWRD2 tWDS tWSW2 tWDH tAH CS7 to CS0 D15 to D0 read HWR LWR write D15 to D0 write T1 tCSD1 tWDD tAD Fi...

Page 719: ...4 page 691 of 1016 REJ09B0138 0600H TW AS A23 to A0 RD read T3 CS7 to CS0 D15 to D0 read HWR LWR write D15 to D0 write T2 tWTS T1 tWTH tWTS tWTH WAIT Figure 22 10 Basic Bus Timing Three State Access w...

Page 720: ...tCSD2 tCSD3 tACC3 tWRD2 tWDD tWDH CS5 to CS2 RAS D15 to D0 read HWR LWR write D15 to D0 write Tr tPCH tAD tCASD tACC4 tRDS tAD tCASD tWRD2 Tp tWCS tWDS tWCH Figure 22 11 DRAM Bus Timing TRc1 CAS TRc2...

Page 721: ...00H TRc CAS TRc tCASD CS5 to CS2 RAS TRr tCASD tCSD2 TRp tCSD2 Figure 22 13 Self Refresh Timing tRSD2 T1 AS A23 to A0 T2 tAH tACC3 tRDS CS0 D15 to D0 read T2 or T3 tAS T1 tASD tASD tRDH tAD RD read Fi...

Page 722: ...SD2 T1 AS A23 to A0 T1 tACC1 CS0 D15 to D0 read T2 or T3 tRDH tAD RD read tRDS Figure 22 15 Burst ROM Access Timing One State Access BREQ A23 to A0 CS7 to CS0 tBRQS tBACD tBZD tBACD tBZD tBRQS BACK AS...

Page 723: ...tions VCC 5 0 V 10 AVCC 5 0 V 10 Vref 4 5 V to AVCC VSS AVSS 0 V 10 to 20 MHz Ta 20 to 75 C regular specifications Ta 40 to 85 C wide range specifications Condition Test Item Symbol Min Max Unit Condi...

Page 724: ...2004 page 696 of 1016 REJ09B0138 0600H AS A23 to A0 RD read CS7 to CS0 D15 to D0 read HWR LWR write D15 to D0 write T2 tDACD1 T1 tDACD2 DACK0 DACK1 Figure 22 18 DMAC Single Address Transfer Timing Tw...

Page 725: ...CS0 D15 to D0 read HWR LWR write D15 to D0 write T3 tDACD1 T2 tDACD2 DACK0 DACK1 T1 Figure 22 19 DMAC Single Address Transfer Timing Three State Access TEND0 TEND1 tTED tTED T1 T2 or T3 Figure 22 20 D...

Page 726: ...igure 22 24 Timer input setup time t TICS 30 Timer clock input setup time t TCKS 30 ns Figure 22 25 Timer clock pulse width Single edge t TCKWH 1 5 t cyc Both edges t TCKWL 2 5 TMR Timer output delay...

Page 727: ...D tPRH tPRS Ports 1 to 3 5 6 A to G write Figure 22 22 I O Port Input Output Timing PO15 to PO0 tPOD Figure 22 23 PPG Output Timing tTICS tTOCD Output compare output Input capture input Note TIOCA0 to...

Page 728: ...22 25 TPU Clock Input Timing TMO0 TMO1 tTMOD Figure 22 26 8 Bit Timer Output Timing TMCI0 TMCI1 tTMCS tTMCS tTMCWH tTMCWL Figure 22 27 8 Bit Timer Clock Input Timing TMRI0 TMRI1 tTMRS Figure 22 28 8...

Page 729: ...e A D conversion characteristics Table 22 9 A D Conversion Characteristics Conditions VCC AVCC 5 0 V 10 Vref 4 5 V to AVCC VSS AVSS 0 V 10 to 20 MHz Ta 20 to 75 C regular specifications Ta 40 to 85 C...

Page 730: ...the microcomputer to an adequate level A capacitor one 0 47 F capacitor or two 0 47 F capacitors connected in parallel should be connected between the VCL pin a pin for internal voltage step down circ...

Page 731: ...7 0 V Analog input voltage VAN 0 3 to AVCC 0 3 V Operating temperature Topr Regular specifications 20 to 75 2 C Wide range specifications 40 to 85 2 C Storage temperature Tstg 55 to 125 C Caution Perm...

Page 732: ...C 0 7 VCC 0 3 V Ports 1 3 5 B to G P60 to P63 PA0 to PA3 2 0 VCC 0 3 V Port 4 2 0 AVCC 0 3 V Input low voltage RES STBY MD2 to MD0 VIL 0 3 0 5 V NMI EXTAL Ports 1 3 to 5 B to G P60 to P63 PA0 to PA3 0...

Page 733: ...4 5 V VIH min VCC 0 9 and VIL max 0 3 V 4 ICC depends on VCC and f as follows ICC max 3 0 mA 0 60 mA MHz V VCC f normal mode ICC max 3 0 mA 0 48 mA MHz V VCC f sleep mode Table 22 13 Permissible Outpu...

Page 734: ...00 The chip Ports 1 A to C LED Figure 22 34 LED Drive Circuit Example 22 3 3 AC Characteristics Figure 22 35 show the test conditions for the AC characteristics C LSI output pin RH RL C 90 pF Ports 1...

Page 735: ...ition Test Item Symbol Min Max Unit Conditions Clock cycle time t cyc 50 100 ns Figure 22 36 Clock high pulse width t CH 20 ns Clock low pulse width t CL 20 ns Clock rise time t Cr 5 ns Clock fall tim...

Page 736: ...4 5 V to AVCC VSS AVSS 0 V 10 to 20 MHz Ta 20 to 75 C regular specifications Ta 40 to 85 C wide range specifications Condition Test Item Symbol Min Max Unit Conditions RES setup time t RESS 200 ns Fig...

Page 737: ...28 2004 page 709 of 1016 REJ09B0138 0600H tRESS tRESW tRESS RES Figure 22 38 Reset Input Timing tIRQS tNMIS tNMIH IRQ Edge input NMI tIRQS tIRQH IRQ IRQ Level input tNMIW tIRQW Figure 22 39 Interrupt...

Page 738: ...S delay time 2 tCSD2 20 ns CS delay time 3 tCSD3 25 ns AS delay time tASD 20 ns RD delay time 1 tRSD1 20 ns RD delay time 2 tRSD2 20 ns CAS delay time tCASD 20 ns Read data setup time tRDS 15 ns Read...

Page 739: ...time tWTS 30 ns Figure 22 42 WAIT hold time tWTH 5 ns BREQ setup time tBRQS 30 ns Figure 22 48 BACK delay time tBACD 15 ns Bus floating time tBZD 50 ns BREQO delay time tBRQOD 30 ns Figure 22 49 tRSD2...

Page 740: ...38 0600H tRSD2 T2 AS A23 to A0 tASD RD read T3 tAS tAH tASD tACC4 tRSD1 tACC5 tAS tRDS tRDH tWRD1 tWRD2 tWDS tWSW2 tWDH tAH CS7 to CS0 D15 to D0 read HWR LWR write D15 to D0 write T1 tCSD1 tWDD tAD Fi...

Page 741: ...4 page 713 of 1016 REJ09B0138 0600H TW AS A23 to A0 RD read T3 CS7 to CS0 D15 to D0 read HWR LWR write D15 to D0 write T2 tWTS T1 tWTH tWTS tWTH WAIT Figure 22 42 Basic Bus Timing Three State Access w...

Page 742: ...tCSD2 tCSD3 tACC3 tWRD2 tWDD tWDH CS5 to CS2 RAS D15 to D0 read HWR LWR write D15 to D0 write Tr tPCH tAD tCASD tACC4 tRDS tAD tCASD tWRD2 Tp tWCS tWDS tWCH Figure 22 43 DRAM Bus Timing TRc1 CAS TRc2...

Page 743: ...00H TRc CAS TRc tCASD CS5 to CS2 RAS TRr tCASD tCSD2 TRp tCSD2 Figure 22 45 Self Refresh Timing tRSD2 T1 AS A23 to A0 T2 tAH tACC3 tRDS CS0 D15 to D0 read T2 or T3 tAS T1 tASD tASD tRDH tAD RD read Fi...

Page 744: ...SD2 T1 AS A23 to A0 T1 tACC1 CS0 D15 to D0 read T2 or T3 tRDH tAD RD read tRDS Figure 22 47 Burst ROM Access Timing One State Access BREQ A23 to A0 CS7 to CS0 tBRQS tBACD tBZD tBACD tBZD tBRQS BACK AS...

Page 745: ...itions VCC 5 0 V 10 AVCC 5 0 V 10 Vref 4 5 V to AVCC VSS AVSS 0 V 10 to 20 MHz Ta 20 to 75 C regular specifications Ta 40 to 85 C wide range specifications Condition Test Item Symbol Min Max Unit Cond...

Page 746: ...2004 page 718 of 1016 REJ09B0138 0600H AS A23 to A0 RD read CS7 to CS0 D15 to D0 read HWR LWR write D15 to D0 write T2 tDACD1 T1 tDACD2 DACK0 DACK1 Figure 22 50 DMAC Single Address Transfer Timing Tw...

Page 747: ...CS0 D15 to D0 read HWR LWR write D15 to D0 write T3 tDACD1 T2 tDACD2 DACK0 DACK1 T1 Figure 22 51 DMAC Single Address Transfer Timing Three State Access TEND0 TEND1 tTED tTED T1 T2 or T3 Figure 22 52 D...

Page 748: ...Figure 22 56 Timer input setup time t TICS 30 Timer clock input setup time t TCKS 30 ns Figure 22 57 Timer clock pulse width Single edge t TCKWH 1 5 t cyc Both edges t TCKWL 2 5 TMR Timer output delay...

Page 749: ...D tPRH tPRS Ports 1 to 3 5 6 A to G write Figure 22 54 I O Port Input Output Timing PO15 to PO0 tPOD Figure 22 55 PPG Output Timing tTICS tTOCD Output compare output Input capture input Note TIOCA0 to...

Page 750: ...22 57 TPU Clock Input Timing TMO0 TMO1 tTMOD Figure 22 58 8 Bit Timer Output Timing TMCI0 TMCI1 tTMCS tTMCS tTMCWH tTMCWL Figure 22 59 8 Bit Timer Clock Input Timing TMRI0 TMRI1 tTMRS Figure 22 60 8...

Page 751: ...e A D conversion characteristics Table 22 19 A D Conversion Characteristics Conditions VCC AVCC 5 0 V 10 Vref 4 5 V to AVCC VSS AVSS 0 V 10 to 20 MHz Ta 20 to 75 C regular specifications Ta 40 to 85 C...

Page 752: ...HD64F2398F20 HD64F2398TE20 Conditions VCC 5 0 V 10 AVCC 5 0 V 10 Vref 4 5 V to AVCC VSS AVSS 0V Ta 0 to 75 C Programming erasing operating temperature regular specifications Ta 0 to 85 C Programming e...

Page 753: ...ting erasing 2 Writing time for 128 bytes indicates the total period in which bit P of flash memory control register 1 FLMCR1 is set Writing verification time is not included 3 Erasing time for one bl...

Page 754: ...t setting 1 4 s Wait time after H FF dummy write 1 2 s Wait time after PV bit clear 1 2 s Wait time after SWE bit clear 1 100 s Maximum programming count 1 4 N 1000 5 Times Erase Wait time after SWE b...

Page 755: ...switching to the masked ROM version 22 5 Usage Note Internal Voltage Step Down for the H8S 2398 F ZTAT The H8S 2398 F ZTAT have a voltage step down circuit that automatically lowers the power supply v...

Page 756: ...specifications 20 to 75 C Wide range specifications 40 to 85 C Storage temperature Tstg 55 to 125 C Caution Permanent damage to the chip may result if absolute maximum rating are exceeded Note ZTAT ve...

Page 757: ...Cin 80 50 15 pF pF pF Vin 0 V f 1 MHz T a 25 C Current dissipation 2 Normal operation I CC 4 78 5 0 V 122 mA f 20 MHz Sleep mode 53 5 0 V 84 mA f 20 MHz Standby 0 01 5 0 A Ta 50 C mode 3 20 0 50 C Ta...

Page 758: ...V Input low voltage RES STBY MD2 to MD0 VIL 0 3 VCC 0 1 V NMI EXTAL Ports 1 3 to 5 B to G P60 to P63 0 3 VCC 0 2 V VCC 4 0 V PA0 to PA3 0 8 VCC 4 0 to 5 5 V Output high All output pins VOH VCC 0 5 V I...

Page 759: ...nd the on chip pull up transistors in the off state 3 The values are for VRAM VCC 2 7 V VIH min VCC 0 9 and VIL max 0 3 V 4 I CC depends on VCC and f as follows I CC max 1 0 mA 1 1 mA MHz V VCC f norm...

Page 760: ...f 1 MHz Ta 25 C Current dissipation 2 Normal operation I CC 4 32 3 3 V 80 mA f 13 MHz Sleep mode 22 3 3 V 55 mA f 13 MHz Standby 0 01 5 0 A Ta 50 C mode 3 20 50 C Ta Analog power supply current Durin...

Page 761: ...cluding ports 1 and A to C I OL 80 mA Total of all output pins including the above 120 mA Permissible output high current per pin All output pins I OH 2 0 mA Permissible output high current total Tota...

Page 762: ...AVCC VSS AVSS 0 V 2 to 20 MHz Ta 20 to 75 C regular specifications Ta 40 to 85 C wide range specifications Condition C VCC 3 0 to 5 5 V AVCC 3 0 to 5 5 V Vref 3 0 V to AVCC VSS AVSS 0 V 2 to 13 MHz T...

Page 763: ...Rev 6 00 Oct 28 2004 page 735 of 1016 REJ09B0138 0600H tCH tCf tcyc tCL tCr Figure 22 68 System Clock Timing tOSC1 tOSC1 EXTAL NMI VCC STBY RES tDEXT tDEXT Figure 22 69 Oscillator Settling Timing...

Page 764: ...20 to 75 C regular specifications Ta 40 to 85 C wide range specifications Condition A Condition B Condition C Test Item Symbol Min Max Min Max Min Max Unit Conditions RES setup time t RESS 200 200 200...

Page 765: ...Rev 6 00 Oct 28 2004 page 737 of 1016 REJ09B0138 0600H tIRQS tNMIS tNMIH IRQ Edge input NMI tIRQS tIRQH IRQi i 0 to 2 IRQ Level input tNMIW tIRQW Figure 22 71 Interrupt Input Timing...

Page 766: ...s setup time tAS 0 5 tcyc 30 0 5 tcyc 15 0 5 tcyc 30 ns Figure 22 79 Address hold time tAH 0 5 tcyc 20 0 5 tcyc 10 0 5 tcyc 20 ns Precharge time tPCH 1 5 tcyc 40 1 5 tcyc 20 1 5 tcyc 40 ns CS delay ti...

Page 767: ...tcyc 20 0 5 tcyc 33 ns Write data hold time tWDH 0 5 tcyc 20 0 5 tcyc 10 0 5 tcyc 20 ns WR setup time tWCS 0 5 tcyc 20 0 5 tcyc 10 0 5 tcyc 20 ns WR hold time tWCH 0 5 tcyc 20 0 5 tcyc 10 0 5 tcyc 20...

Page 768: ...B0138 0600H tRSD2 T1 tAD AS A23 to A0 tASD RD read T2 tCSD1 tAS tAH tASD tACC2 tAS tAS tRSD1 tACC3 tRDS tRDH tWRD2 tWRD2 tWDD tWSW1 tWDH tAH CS7 to CS0 D15 to D0 read HWR LWR write D15 to D0 write Fig...

Page 769: ...38 0600H tRSD2 T2 AS A23 to A0 tASD RD read T3 tAS tAH tASD tACC4 tRSD1 tACC5 tAS tRDS tRDH tWRD1 tWRD2 tWDS tWSW2 tWDH tAH CS7 to CS0 D15 to D0 read HWR LWR write D15 to D0 write T1 tCSD1 tWDD tAD Fi...

Page 770: ...4 page 742 of 1016 REJ09B0138 0600H TW AS A23 to A0 RD read T3 CS7 to CS0 D15 to D0 read HWR LWR write D15 to D0 write T2 tWTS T1 tWTH tWTS tWTH WAIT Figure 22 74 Basic Bus Timing Three State Access w...

Page 771: ...tCSD2 tCSD3 tACC3 tWRD2 tWDD tWDH CS5 to CS2 RAS D15 to D0 read HWR LWR write D15 to D0 write Tr tPCH tAD tCASD tACC4 tRDS tAD tCASD tWRD2 Tp tWCS tWDS tWCH Figure 22 75 DRAM Bus Timing TRc1 CAS TRc2...

Page 772: ...00H TRc CAS TRc tCASD CS5 to CS2 RAS TRr tCASD tCSD2 TRp tCSD2 Figure 22 77 Self Refresh Timing tRSD2 T1 AS A23 to A0 T2 tAH tACC3 tRDS CS0 D15 to D0 read T2 or T3 tAS T1 tASD tASD tRDH tAD RD read Fi...

Page 773: ...SD2 T1 AS A23 to A0 T1 tACC1 CS0 D15 to D0 read T2 or T3 tRDH tAD RD read tRDS Figure 22 79 Burst ROM Access Timing One State Access BREQ A23 to A0 CS7 to CS0 tBRQS tBACD tBZD tBACD tBZD tBRQS BACK AS...

Page 774: ...Vref 4 5 V to AVCC VSS AVSS 0 V 2 to 20 MHz Ta 20 to 75 C regular specifications Ta 40 to 85 C wide range specifications Condition C VCC 3 0 to 5 5 V AVCC 3 0 to 5 5 V Vref 3 0 V to AVCC VSS AVSS 0 V...

Page 775: ...2004 page 747 of 1016 REJ09B0138 0600H AS A23 to A0 RD read CS7 to CS0 D15 to D0 read HWR LWR write D15 to D0 write T2 tDACD1 T1 tDACD2 DACK0 DACK1 Figure 22 82 DMAC Single Address Transfer Timing Tw...

Page 776: ...CS0 D15 to D0 read HWR LWR write D15 to D0 write T3 tDACD1 T2 tDACD2 DACK0 DACK1 T1 Figure 22 83 DMAC Single Address Transfer Timing Three State Access TEND0 TEND1 tTED tTED T1 T2 or T3 Figure 22 84 D...

Page 777: ...data delay time t PWD 100 50 75 ns Figure 22 86 Input data setup time t PRS 50 30 50 Input data hold time t PRH 50 30 50 PPG Pulse output delay time t POD 100 50 75 ns Figure 22 87 TPU Timer output d...

Page 778: ...TXD 100 50 75 ns Figure 22 95 Receive data setup time synchronous t RXS 100 50 75 ns Receive data hold time synchronous t RXH 100 50 75 ns A D con verter Trigger input setup time t TRGS 50 30 50 ns F...

Page 779: ...TIOCA0 to TIOCA5 TIOCB0 to TIOCB5 TIOCC0 TIOCC3 TIOCD0 TIOCD3 Figure 22 88 TPU Input Output Timing tTCKS tTCKS TCLKA to TCLKD tTCKWH tTCKWL Figure 22 89 TPU Clock Input Timing TMO0 TMO1 tTMOD Figure...

Page 780: ...WOVD tWOVD Figure 22 93 WDT Output Timing SCK0 to SCK2 tSCKW tSCKr tSCKf tScyc Figure 22 94 SCK Clock Input Timing TxD0 to TxD2 transmit data RxD0 to RxD2 receive data SCK0 to SCK2 tRXS tRXH tTXD Figu...

Page 781: ...range specifications Condition C VCC AVCC 3 0 to 5 5 V Vref 3 0 V to AVCC VSS AVSS 0 V 2 to 13 MHz Ta 20 to 75 C regular specifications Ta 40 to 85 C wide range specifications Condition A Condition B...

Page 782: ...5 0 V 10 Vref 4 5 V to AVCC VSS AVSS 0 V 2 to 20 MHz Ta 20 to 75 C regular specifications Ta 40 to 85 C wide range specifications Condition C VCC AVCC 3 0 to 5 5 V Vref 3 0 V to AVCC VSS AVSS 0 V 2 t...

Page 783: ...olute maximum rating are exceeded Notes 1 12 V must not be applied to any pin as this will cause permanent damage to the chip 2 The operating temperature ranges for flash memory programming erasing ar...

Page 784: ...urrent dissipation 2 Normal operation I CC 4 78 5 0 V 122 mA f 20 MHz Sleep mode 53 5 0 V 84 mA f 20 MHz Standby 0 01 5 0 A Ta 50 C mode 3 20 0 50 C Ta Flash memory programming erasing 88 5 0 V 122 mA...

Page 785: ...Input low voltage RES STBY MD2 to MD0 FWE VIL 0 3 VCC 0 1 V NMI EXTAL Ports 1 3 to 5 B to G P60 to P63 0 3 VCC 0 2 V VCC 4 0 V PA0 to PA3 0 8 VCC 4 0 to 5 5 V Output high All output pins VOH VCC 0 5...

Page 786: ...3 The values are for VRAM VCC 3 0 V VIH min VCC 0 9 and VIL max 0 3 V 4 I CC depends on VCC and f as follows I CC max 1 0 mA 1 1 mA MHz V VCC f normal mode I CC max 1 0 mA 0 75 mA MHz V VCC f sleep mo...

Page 787: ...0 V 2 to 13 MHz Ta 20 to 75 C regular specifications Ta 40 to 85 C wide range specifications Condition B Condition C Item Symbol Min Max Min Max Unit Test Conditions Clock cycle time t cyc 50 500 76...

Page 788: ...3 0 to 5 5 V Vref 3 0 V to AVCC VSS AVSS 0 V 2 to 13 MHz Ta 20 to 75 C regular specifications Ta 40 to 85 C wide range specifications Condition B Condition C Item Symbol Min Max Min Max Unit Test Cond...

Page 789: ...ld time t AH 0 5 t cyc 10 0 5 t cyc 20 ns Precharge time t PCH 1 5 t cyc 20 1 5 t cyc 40 ns CS delay time 1 t CSD1 20 40 ns CS delay time 2 t CSD2 20 40 ns CS delay time 3 t CSD3 25 40 ns AS delay tim...

Page 790: ...delay time t BACD 15 30 ns Bus floating time t BZD 50 100 ns BREQO delay time t BRQOD 30 60 ns Figure 22 81 4 DMAC Timing Table 22 39 lists the DMAC timing Table 22 39 DMAC Timing Condition B VCC 5 0...

Page 791: ...5 ns Figure 22 86 Input data setup time t PRS 30 50 Input data hold time t PRH 30 50 PPG Pulse output delay time t POD 50 75 ns Figure 22 87 TPU Timer output delay time t TOCD 50 75 ns Figure 22 88 Ti...

Page 792: ...AVCC 5 0 V 10 Vref 4 5 V to AVCC VSS AVSS 0 V 2 to 20 MHz Ta 20 to 75 C regular specifications Ta 40 to 85 C wide range specifications Condition C VCC AVCC 3 0 V to 5 5 V Vref 3 0 V to AVCC VSS AVSS...

Page 793: ...2 0 3 0 LSB 2 M resistive load 1 0 2 0 LSB 4 M resistive load 22 7 6 Flash Memory Characteristics Table 22 43 shows the flash memory characteristics Table 22 43 Flash Memory Characteristics 1 Conditio...

Page 794: ...me tp max wait time after P bit setting z maximum programming count N 5 Number of times when the wait time after P bit setting z 200 s The maximum number of writes N should be set according to the act...

Page 795: ...ase count 1 6 N 120 240 Times Notes 1 Set the times according to the program erase algorithms 2 Programming time per 32 bytes Shows the total time the flash memory control register FLMCR is set It doe...

Page 796: ...manual due to differences in the fabrication process the on chip ROM and the layout patterns there will be differences in the actual values of the electrical characteristics the operating margins the...

Page 797: ...er IMM Immediate data disp Displacement Add Subtract Multiply Divide Logical AND Logical OR Logical exclusive OR Transfer from the operand on the left to the operand on the right or transition from th...

Page 798: ...MOV B aa 32 Rd B 6 MOV B Rs ERd B 2 MOV B Rs d 16 ERd B 4 MOV B Rs d 32 ERd B 8 MOV B Rs ERd B 2 MOV B Rs aa 8 B 2 MOV B Rs aa 16 B 4 MOV B Rs aa 32 B 6 MOV W xx 16 Rd W 4 MOV W Rs Rd W 2 MOV W ERs R...

Page 799: ...W 6 MOV L xx 32 ERd L 6 MOV L ERs ERd L 2 MOV L ERs ERd L 4 MOV L d 16 ERs ERd L 6 MOV L d 32 ERs ERd L 10 MOV L ERs ERd L 4 MOV L aa 16 ERd L 6 MOV L aa 32 ERd L 8 d 16 ERs Rd16 0 3 d 32 ERs Rd16 0 5...

Page 800: ...Rn W 2 PUSH L ERn L 4 LDM SP ERm ERn L 4 STM ERm ERn SP L 4 MOVFPE aa 16 Rd MOVTPE Rs aa 16 ERs32 ERd 0 4 ERs32 d 16 ERd 0 5 ERs32 d 32 ERd 0 7 ERd32 4 ERd32 ERs32 ERd 0 5 ERs32 aa 16 0 5 ERs32 aa 32...

Page 801: ...1 ERd L 2 ADDS 2 ERd L 2 ADDS 4 ERd L 2 INC B Rd B 2 INC W 1 Rd W 2 INC W 2 Rd W 2 INC L 1 ERd L 2 INC L 2 ERd L 2 DAA Rd B 2 SUB B Rs Rd B 2 SUB W xx 16 Rd W 4 Rd8 xx 8 Rd8 1 Rd8 Rs8 Rd8 1 Rd16 xx 16...

Page 802: ...L 2 DEC L 2 ERd L 2 DAS Rd B 2 MULXU B Rs Rd B 2 MULXU W Rs ERd W 2 MULXS B Rs Rd B 4 MULXS W Rs ERd W 4 Rd16 Rs16 Rd16 3 1 ERd32 xx 32 ERd32 4 3 ERd32 ERs32 ERd32 4 1 Rd8 xx 8 C Rd8 5 1 Rd8 Rs8 C Rd8...

Page 803: ...d B 2 NEG W Rd W 2 NEG L ERd L 2 EXTU W Rd W 2 EXTU L ERd L 2 Rd16 Rs8 Rd16 RdH remainder 6 7 12 RdL quotient unsigned division ERd32 Rs16 ERd32 Ed remainder 6 7 20 Rd quotient unsigned division Rd16...

Page 804: ...S MAC CLRMAC LDMAC STMAC EXTS W Rd W 2 EXTS L ERd L 2 TAS ERd 3 B 4 MAC ERn ERm CLRMAC LDMAC ERs MACH LDMAC ERs MACL STMAC MACH ERd STMAC MACL ERd bit 7 of Rd16 0 1 bit 15 to 8 of Rd16 bit 15 of ERd32...

Page 805: ...XOR B xx 8 Rd B 2 XOR B Rs Rd B 2 XOR W xx 16 Rd W 4 XOR W Rs Rd W 2 XOR L xx 32 ERd L 6 XOR L ERs ERd L 4 NOT B Rd B 2 NOT W Rd W 2 NOT L ERd L 2 Rd8 xx 8 Rd8 0 1 Rd8 Rs8 Rd8 0 1 Rd16 xx 16 Rd16 0 2...

Page 806: ...2 Rd B 2 SHAL W Rd W 2 SHAL W 2 Rd W 2 SHAL L ERd L 2 SHAL L 2 ERd L 2 SHAR B Rd B 2 SHAR B 2 Rd B 2 SHAR W Rd W 2 SHAR W 2 Rd W 2 SHAR L ERd L 2 SHAR L 2 ERd L 2 SHLL B Rd B 2 SHLL B 2 Rd B 2 SHLL W...

Page 807: ...R W 2 Rd W 2 SHLR L ERd L 2 SHLR L 2 ERd L 2 ROTXL B Rd B 2 ROTXL B 2 Rd B 2 ROTXL W Rd W 2 ROTXL W 2 Rd W 2 ROTXL L ERd L 2 ROTXL L 2 ERd L 2 ROTXR B Rd B 2 ROTXR B 2 Rd B 2 ROTXR W Rd W 2 ROTXR W 2...

Page 808: ...Bytes Operand Size xx Rn ERn d ERn ERn ERn aa d PC aa Mnemonic ROTL ROTR ROTL B Rd B 2 ROTL B 2 Rd B 2 ROTL W Rd W 2 ROTL W 2 Rd W 2 ROTL L ERd L 2 ROTL L 2 ERd L 2 ROTR B Rd B 2 ROTR B 2 Rd B 2 ROTR...

Page 809: ...6 BSET Rn aa 32 B 8 BCLR xx 3 Rd B 2 BCLR xx 3 ERd B 4 BCLR xx 3 aa 8 B 4 BCLR xx 3 aa 16 B 6 BCLR xx 3 aa 32 B 8 BCLR Rn Rd B 2 BCLR Rn ERd B 4 BCLR Rn aa 8 B 4 BCLR Rn aa 16 B 6 xx 3 of Rd8 1 1 xx 3...

Page 810: ...4 BNOT Rn aa 16 B 6 BNOT Rn aa 32 B 8 BTST xx 3 Rd B 2 BTST xx 3 ERd B 4 BTST xx 3 aa 8 B 4 BTST xx 3 aa 16 B 6 Rn8 of aa 32 0 6 xx 3 of Rd8 xx 3 of Rd8 1 xx 3 of ERd 4 xx 3 of ERd xx 3 of aa 8 4 xx 3...

Page 811: ...6 BLD xx 3 aa 32 B 8 BILD xx 3 Rd B 2 BILD xx 3 ERd B 4 BILD xx 3 aa 8 B 4 BILD xx 3 aa 16 B 6 BILD xx 3 aa 32 B 8 BST xx 3 Rd B 2 BST xx 3 ERd B 4 BST xx 3 aa 8 B 4 xx 3 of aa 32 Z 5 Rn8 of Rd8 Z 1 R...

Page 812: ...3 aa 16 B 6 BAND xx 3 aa 32 B 8 BIAND xx 3 Rd B 2 BIAND xx 3 ERd B 4 BIAND xx 3 aa 8 B 4 BIAND xx 3 aa 16 B 6 BIAND xx 3 aa 32 B 8 BOR xx 3 Rd B 2 BOR xx 3 ERd B 4 C xx 3 of aa 16 5 C xx 3 of aa 32 6...

Page 813: ...OR xx 3 aa 8 B 4 BXOR xx 3 aa 16 B 6 BXOR xx 3 aa 32 B 8 BIXOR xx 3 Rd B 2 BIXOR xx 3 ERd B 4 BIXOR xx 3 aa 8 B 4 BIXOR xx 3 aa 16 B 6 BIXOR xx 3 aa 32 B 8 C xx 3 of aa 8 C 3 C xx 3 of aa 16 C 4 C xx...

Page 814: ...C 0 2 3 C 1 2 3 Z 0 2 3 Z 1 2 3 V 0 2 3 Operation Condition Code Branching Condition I H N Z V C Advanced No of States 1 BRA d 8 BT d 8 2 if condition is true then BRA d 16 BT d 16 4 PC PC d BRN d 8...

Page 815: ...Rn ERn aa d PC aa Mnemonic Bcc V 1 2 3 N 0 2 3 N 1 2 3 N V 0 2 3 N V 1 2 3 Z N V 0 2 3 Z N V 1 2 3 Operation Condition Code Branching Condition I H N Z V C Advanced No of States 1 BVS d 8 2 BVS d 16 4...

Page 816: ...n ERn ERn aa d PC aa Mnemonic JMP BSR JSR RTS JMP ERn 2 JMP aa 24 4 JMP aa 8 2 BSR d 8 2 BSR d 16 4 JSR ERn 2 JSR aa 24 4 JSR aa 8 2 RTS 2 PC ERn 2 PC aa 24 3 PC aa 8 5 PC SP PC PC d 8 4 PC SP PC PC d...

Page 817: ...LDC d 16 ERs EXR W 6 LDC d 32 ERs CCR W 10 LDC d 32 ERs EXR W 10 LDC ERs CCR W 4 LDC ERs EXR W 4 LDC aa 16 CCR W 6 LDC aa 16 EXR W 6 LDC aa 32 CCR W 8 LDC aa 32 EXR W 8 PC SP CCR SP 1 8 9 EXR SP vecto...

Page 818: ...Rd W 4 STC CCR aa 16 W 6 STC EXR aa 16 W 6 STC CCR aa 32 W 8 STC EXR aa 32 W 8 ANDC xx 8 CCR B 2 ANDC xx 8 EXR B 4 ORC xx 8 CCR B 2 ORC xx 8 EXR B 4 XORC xx 8 CCR B 2 XORC xx 8 EXR B 4 NOP 2 CCR Rd8 1...

Page 819: ...sters 2 Cannot be used in the H8S 2357 Series 3 Set to 1 when a carry or borrow occurs at bit 11 otherwise cleared to 0 4 Set to 1 when a carry or borrow occurs at bit 27 otherwise cleared to 0 5 Reta...

Page 820: ...2 BRA d 8 BT d 8 BRA d 16 BT d 16 BRN d 8 BF d 8 BRN d 16 BF d 16 Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc ti...

Page 821: ...d 16 BGT d 8 BGT d 16 BLE d 8 BLE d 16 Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion Bcc 4 5 4 5 4 5 4 5 4 5...

Page 822: ...e 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion BCLR BIAND BILD BIOR B B B B B B B B B B B B B B B B B B B B B B B B B 0 0 0 1 0 1 0 1 0 IMM erd erd IMM erd IMM...

Page 823: ...3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion BIST BIXOR BLD BNOT B B B B B B B B B B B B B B B B B B B B B B B B B 1 0 1 0 0 0 0 0 0 IMM erd IMM erd IMM erd IM...

Page 824: ...yte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion BOR BSET BSR BST BTST B B B B B B B B B B B B B B B B B B B B B B B B B B B 0 0 0 0 0 0 0 0 0 0 IMM erd IMM erd erd IMM erd IMM...

Page 825: ...byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion BTST BXOR CLRMAC CMP DAA DAS DEC DIVXS DIVXU EEPMOV B B B B B B B B B B W W L L B B B W W L L B W B...

Page 826: ...ction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion EXTS EXTU INC JMP JSR LDC W L W L B W W L L B B B B W W W W W W W W W W 0 0 ern ern...

Page 827: ...d 16 ERs Rd MOV W d 32 ERs Rd Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion LDC LDM LDMAC MAC MOV W W L L L L...

Page 828: ...d byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion MOV MOVFPE MOVTPE MULXS MULXU W W W W W W W W W L L L L L L L L L L L L L L B B B W B W 0 1 1 0 1 1 ers erd erd erd...

Page 829: ...L 2 ERd Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion NEG NOP NOT OR ORC POP PUSH ROTL B W L B W L B B W W L...

Page 830: ...d SHAL W 2 Rd SHAL L ERd SHAL L 2 ERd Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion ROTR ROTXL ROTXR RTE RTS...

Page 831: ...d Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion SHAR SHLL SHLR SLEEP STC B B W W L L B B W W L L B B W W L L...

Page 832: ...onic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion STC STM STMAC SUB SUBS SUBX TAS TRAPA XOR W W W W L L L L L B W W L...

Page 833: ...gister Field General Register Register Field General Register 000 001 111 ER0 ER1 ER7 0000 0001 0111 1000 1001 1111 R0 R1 R7 E0 E1 E7 0000 0001 0111 1000 1001 1111 R0H R1H R7H R0L R1L R7L 16 Bit Regis...

Page 834: ...XU BNOT 2 BHI MULXU BCLR 3 BLS DIVXU BTST STC STMAC LDC LDMAC 4 ORC OR BCC RTS OR BOR BIOR 6 ANDC AND BNE RTE AND 5 XORC XOR BCS BSR XOR BXOR BIXOR BAND BIAND 7 LDC BEQ TRAPA BST BIST BLD BILD 8 BVC M...

Page 835: ...UB 4 SHLL SHLR ROTXL ROTXR BCC MOVFPE OR OR 5 INC EXTU DEC BCS XOR XOR 6 MAC BNE AND AND 7 INC SHLL SHLR ROTXL ROTXR EXTU DEC BEQ LDC STC 8 SLEEP BVC MOV ADDS SHAL SHAR ROTL ROTR NEG SUBS 9 BVS A CLRM...

Page 836: ...t of DH is 0 Instruction when most significant bit of DH is 1 Notes AH AL BH BL CH CL 01C05 01D05 01F06 7Cr06 1 7Cr07 1 7Dr06 1 7Dr07 1 7Eaa6 2 7Eaa7 2 7Faa6 2 7Faa7 2 0 MULXS BSET BSET BSET BSET 1 DI...

Page 837: ...ost significant bit of HH is 0 Instruction when most significant bit of HH is 1 Note aa is the absolute address specification 5th byte 6th byte EH EL FH FL 7th byte 8th byte GH GL HH HL 6A10aaaa6 6A10...

Page 838: ...pporting modules accessed in two states with 8 bit bus width external devices accessed in three states with one wait state and 16 bit bus width 1 BSET 0 FFFFC7 8 From table A 5 I L 2 J K M N 0 From ta...

Page 839: ...Rd 1 ADDS ADDS 1 2 4 ERd 1 ADDX ADDX xx 8 Rd 1 ADDX Rs Rd 1 AND AND B xx 8 Rd 1 AND B Rs Rd 1 AND W xx 16 Rd 2 AND W Rs Rd 1 AND L xx 32 ERd 3 AND L ERs ERd 2 ANDC ANDC xx 8 CCR 1 ANDC xx 8 EXR 2 BAND...

Page 840: ...16 2 1 BCLR BCLR xx 3 Rd 1 BCLR xx 3 ERd 2 2 BCLR xx 3 aa 8 2 2 BCLR xx 3 aa 16 3 2 BCLR xx 3 aa 32 4 2 BCLR Rn Rd 1 BCLR Rn ERd 2 2 BCLR Rn aa 8 2 2 BCLR Rn aa 16 3 2 BCLR Rn aa 32 4 2 BIAND BIAND xx...

Page 841: ...BNOT BNOT xx 3 Rd 1 BNOT xx 3 ERd 2 2 BNOT xx 3 aa 8 2 2 BNOT xx 3 aa 16 3 2 BNOT xx 3 aa 32 4 2 BNOT Rn Rd 1 BNOT Rn ERd 2 2 BNOT Rn aa 8 2 2 BNOT Rn aa 16 3 2 BNOT Rn aa 32 4 2 BOR BOR xx 3 Rd 1 BOR...

Page 842: ...32 4 1 BXOR BXOR xx 3 Rd 1 BXOR xx 3 ERd 2 1 BXOR xx 3 aa 8 2 1 BXOR xx 3 aa 16 3 1 BXOR xx 3 aa 32 4 1 CLRMAC CLRMAC Cannot be used in the H8S 2357 Group CMP CMP B xx 8 Rd 1 CMP B Rs Rd 1 CMP W xx 1...

Page 843: ...6 ERs CCR 3 1 LDC d 16 ERs EXR 3 1 LDC d 32 ERs CCR 5 1 LDC d 32 ERs EXR 5 1 LDC ERs CCR 2 1 1 LDC ERs EXR 2 1 1 LDC aa 16 CCR 3 1 LDC aa 16 EXR 3 1 LDC aa 32 CCR 4 1 LDC aa 32 EXR 4 1 LDM LDM L SP ER...

Page 844: ...MOV W Rs ERd 1 1 MOV W Rs d 16 ERd 2 1 MOV W Rs d 32 ERd 4 1 MOV W Rs ERd 1 1 1 MOV W Rs aa 16 2 1 MOV W Rs aa 32 3 1 MOV L xx 32 ERd 3 MOV L ERs ERd 1 MOV L ERs ERd 2 2 MOV L d 16 ERs ERd 3 2 MOV L...

Page 845: ...L ERs ERd 2 ORC ORC xx 8 CCR 1 ORC xx 8 EXR 2 POP POP W Rn 1 1 1 POP L ERn 2 2 1 PUSH PUSH W Rn 1 1 1 PUSH L ERn 2 2 1 ROTL ROTL B Rd 1 ROTL B 2 Rd 1 ROTL W Rd 1 ROTL W 2 Rd 1 ROTL L ERd 1 ROTL L 2 ER...

Page 846: ...W Rd 1 SHAR W 2 Rd 1 SHAR L ERd 1 SHAR L 2 ERd 1 SHLL SHLL B Rd 1 SHLL B 2 Rd 1 SHLL W Rd 1 SHLL W 2 Rd 1 SHLL L ERd 1 SHLL L 2 ERd 1 SHLR SHLR B Rd 1 SHLR B 2 Rd 1 SHLR W Rd 1 SHLR W 2 Rd 1 SHLR L ER...

Page 847: ...57 Group STMAC MACL ERd SUB SUB B Rs Rd 1 SUB W xx 16 Rd 2 SUB W Rs Rd 1 SUB L xx 32 ERd 3 SUB L ERs ERd 1 SUBS SUBS 1 2 4 ERd 1 SUBX SUBX xx 8 Rd 1 SUBX Rs Rd 1 TAS TAS ERd 3 2 2 TRAPA TRAPA x 2 Adva...

Page 848: ...End of instruction Order of execution Read effective address word size read No read or write Read 2nd word of current instruction word size read Legend R B Byte size read R W Word size read W B Byte...

Page 849: ...ith an 8 bit bus using three state access with no wait states Address bus RD HWR LWR R W 2nd Fetching 2nd byte of instruction at jump address Fetching 1nd byte of instruction at jump address Fetching...

Page 850: ...NDC xx 8 EXR R W 2nd R W NEXT BAND xx 3 Rd R W NEXT BAND xx 3 ERd R W 2nd R B EA R W M NEXT BAND xx 3 aa 8 R W 2nd R B EA R W M NEXT BAND xx 3 aa 16 R W 2nd R W 3rd R B EA R W M NEXT BAND xx 3 aa 32 R...

Page 851: ...W EA 1 state BEQ d 16 R W 2nd Internal operation R W EA 1 state BVC d 16 R W 2nd Internal operation R W EA 1 state BVS d 16 R W 2nd Internal operation R W EA 1 state BPL d 16 R W 2nd Internal operatio...

Page 852: ...2nd R W 3rd R W 4th R B EA R W M NEXT BIOR xx 3 Rd R W NEXT BIOR xx 3 ERd R W 2nd R B EA R W M NEXT BIOR xx 3 aa 8 R W 2nd R B EA R W M NEXT BIOR xx 3 aa 16 R W 2nd R W 3rd R B EA R W M NEXT BIOR xx...

Page 853: ...3 Rd R W NEXT BSET xx 3 ERd R W 2nd R B M EA R W M NEXT W B EA BSET xx 3 aa 8 R W 2nd R B M EA R W M NEXT W B EA BSET xx 3 aa 16 R W 2nd R W 3rd R B M EA R W M NEXT W B EA BSET xx 3 aa 32 R W 2nd R W...

Page 854: ...nd R W 3rd R W 4th R B EA R W M NEXT CLRMAC Cannot be used in the H8S 2357 Group CMP B xx 8 Rd R W NEXT CMP B Rs Rd R W NEXT CMP W xx 16 Rd R W 2nd R W NEXT CMP W Rs Rd R W NEXT CMP L xx 32 ERd R W 2n...

Page 855: ...EXT LDC Rs EXR R W NEXT LDC ERs CCR R W 2nd R W NEXT R W EA LDC ERs EXR R W 2nd R W NEXT R W EA LDC d 16 ERs CCR R W 2nd R W 3rd R W NEXT R W EA LDC d 16 ERs EXR R W 2nd R W 3rd R W NEXT R W EA LDC d...

Page 856: ...te MOV B aa 8 Rd R W NEXT R B EA MOV B aa 16 Rd R W 2nd R W NEXT R B EA MOV B aa 32 Rd R W 2nd R W 3rd R W NEXT R B EA MOV B Rs ERd R W NEXT W B EA MOV B Rs d 16 ERd R W 2nd R W NEXT W B EA MOV B Rs d...

Page 857: ...L aa 32 ERd R W 2nd R W M 3rd R W 4th R W NEXT R W M EA R W EA 2 MOV L ERs ERd R W 2nd R W M NEXT W W M EA W W EA 2 MOV L ERs d 16 ERd R W 2nd R W M 3rd R W NEXT W W M EA W W EA 2 MOV L ERs d 32 ERd...

Page 858: ...operation W W EA 1 state PUSH L ERn R W 2nd R W M NEXT Internal operation W W M EA W W EA 2 1 state ROTL B Rd R W NEXT ROTL B 2 Rd R W NEXT ROTL W Rd R W NEXT ROTL W 2 Rd R W NEXT ROTL L ERd R W NEXT...

Page 859: ...W NEXT SHAR B 2 Rd R W NEXT SHAR W Rd R W NEXT SHAR W 2 Rd R W NEXT SHAR L ERd R W NEXT SHAR L 2 ERd R W NEXT SHLL B Rd R W NEXT SHLL B 2 Rd R W NEXT SHLL W Rd R W NEXT SHLL W 2 Rd R W NEXT SHLL L ER...

Page 860: ...tack H 3 W W stack L 3 1 state STM L ERn ERn 2 SP R W 2nd R W M NEXT Internal operation W W M stack H 3 W W stack L 3 1 state STM L ERn ERn 3 SP R W 2nd R W M NEXT Internal operation W W M stack H 3 W...

Page 861: ...ents of ER6 Both registers are incremented by 1 after execution of the instruction n is the initial value of R4L or R4 If n 0 these bus cycles are not executed 3 Repeated two times to save or restore...

Page 862: ...erands 15 for word operands 7 for byte operands Si Di Ri Dn 0 1 Z C The i th bit of the source operand The i th bit of the destination operand The i th bit of the result The specified bit in the desti...

Page 863: ...Rm 4 N Rm Z Z Rm R0 V Sm Dm Rm Sm Dm Rm C Sm Dm Dm Rm Sm Rm AND 0 N Rm Z Rm Rm 1 R0 ANDC Stores the corresponding bits of the result No flags change when the operand is EXR BAND C C Dn Bcc BCLR BIAND...

Page 864: ...Dm Z Sm Sm 1 S0 DIVXU N Sm Z Sm Sm 1 S0 EEPMOV EXTS 0 N Rm Z Rm Rm 1 R0 EXTU 0 0 Z Rm Rm 1 R0 INC N Rm Z Rm Rm 1 R0 V Dm Rm JMP JSR LDC Stores the corresponding bits of the result No flags change when...

Page 865: ...R0 C D0 1 bit shift or C D1 2 bit shift ROTXL 0 N Rm Z Rm Rm 1 R0 C Dm 1 bit shift or C Dm 1 2 bit shift ROTXR 0 N Rm Z Rm Rm 1 R0 C D0 1 bit shift or C D1 2 bit shift RTE Stores the corresponding bi...

Page 866: ...UB H Sm 4 Dm 4 Dm 4 Rm 4 Sm 4 Rm 4 N Rm Z Rm Rm 1 R0 V Sm Dm Rm Sm Dm Rm C Sm Dm Dm Rm Sm Rm SUBS SUBX H Sm 4 Dm 4 Dm 4 Rm 4 Sm 4 Rm 4 N Rm Z Z Rm R0 V Sm Dm Rm Sm Dm Rm C Sm Dm Dm Rm Sm Rm TAS 0 N Dm...

Page 867: ...MD3 MD2 MD1 MD0 H FE82 TIOR3H IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H FE83 TIOR3L IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 H FE84 TIER3 TTGE TCIEV TGIED TGIEC TGIEB TGIEA H FE85 TSR3 TCFV TGFD TGFC T...

Page 868: ...DDR PD2DDR PD1DDR PD0DDR H FEBD PEDDR PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR H FEBE PFDDR PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR H FEBF PGDDR PG4DDRPG3DDRPG2DDRPG1DDR...

Page 869: ...F8 MAR1BH H FEF9 H FEFA MAR1BL H FEFB H FEFC IOAR1B H FEFD H FEFE ETCR1B H FEFF H FF00 DMAWER WE1B WE1A WE0B WE0A 8 bits H FF01 DMATCR TEE1 TEE0 H FF02 DMACR0A DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0...

Page 870: ...ts H FF3C MSTPCRH MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 Power down 8 bits H FF3D MSTPCRL MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 mode H FF42 SYSCR2 8 FLSHE MCU 8 bits H FF44 Re...

Page 871: ...PCR 2 PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR H FF71 PBPCR 2 PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR H FF72 PCPCR 2 PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0...

Page 872: ...A6 DACR DAOE1 DAOE0 DAE H FFAC Reserved Reserved H FFB0 TCR0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 8 bit timer 16 bits H FFB1 TCR1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 channel 0 1 H FFB2...

Page 873: ...EG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU2 16 bits H FFF1 TMDR2 MD3 MD2 MD1 MD0 H FFF2 TIOR2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H FFF4 TIER2 TTGE TCIEU TCIEV TGIEB TGIEA H FFF5 TSR2 TCFD TCFU TCFV TGFB TGF...

Page 874: ...Rev 6 00 Oct 28 2004 page 846 of 1016 REJ09B0138 0600H 6 Applies to the H8S 2357 ZTAT only 7 Applies to the H8S 2357 F ZTAT only 8 Applies to the H8S 2398 F ZTAT only...

Page 875: ...Mode 0 1 Normal mode Repeat mode Block transfer mode 0 1 0 1 DTC Data Transfer Size 0 1 Byte size transfer DTC Transfer Mode Select 0 1 Word size transfer Destination side is repeat area or block area...

Page 876: ...e Read Write 22 21 20 19 4 3 2 1 0 Specifies transfer data source address Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined DAR DTC Destinat...

Page 877: ...e match input capture 2 TCNT cleared by TGRD compare match input capture 2 Counter Clear 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock Edge 0 1 Count at rising edge Count at falling edge Count at both edges I...

Page 878: ...tes normally 0 1 Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Mode 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Notes 1 2 Don...

Page 879: ...put capture register Initial output is 0 output Output disabled Initial output is 1 output Capture input source is TIOCA3 pin Capture input source is channel 4 count clock Input capture at TCNT4 count...

Page 880: ...ompare match Initial output is 1 output Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input source is TIOCC3 pin TGR3C is input capture register Captur...

Page 881: ...nterrupt requests TCIV by TCFV disabled Interrupt requests TCIV by TCFV enabled Overflow Interrupt Enable TGR Interrupt Enable D TGR Interrupt Enable C TGR Interrupt Enable B 0 1 Interrupt requests TG...

Page 882: ...Clearing conditions When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 When 0 is written to TGFA...

Page 883: ...sing edge Count at falling edge Count at both edges Internal clock counts on 1 Internal clock counts on 4 Internal clock counts on 16 Internal clock counts on 64 External clock counts on TCLKA pin inp...

Page 884: ...ed PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Mode 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Note Don t care 7 1 6 1 5 0 4 0 3 MD3 0 R W 0 MD0 0 R...

Page 885: ...ut at compare match Initial output is 1 output Input capture at rising edge Input capture at falling edge Input capture at both edges TGR4A is input capture register Capture input source is TIOCA4 pin...

Page 886: ...Interrupt requests TGIA by TGFA bit enabled Interrupt requests TGIB by TGFB bit disabled Interrupt requests TGIB by TGFB bit enabled TGR Interrupt Enable B Interrupt requests TCIV by TCFV disabled In...

Page 887: ...Input Capture Output Compare Flag A 1 Setting conditions Note Can only be written with 0 for flag clearing When TCNT TGRA while TGRA is functioning as output compare register When TCNT value is trans...

Page 888: ...on 16 Internal clock counts on 64 External clock counts on TCLKA pin input External clock counts on TCLKC pin input Internal clock counts on 256 External clock counts on TCLKD pin input Time Prescaler...

Page 889: ...ed PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Mode 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Note MD3 is a reserved bit In a write it should always...

Page 890: ...Initial output is 0 output Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match Initial output is 1 output Input capture at rising edge Input capture at...

Page 891: ...ation enabled A D Conversion Start Request Enable 0 1 Interrupt requests TCIU by TCFU disabled Interrupt requests TCIU by TCFU enabled Underflow Interrupt Enable TGR Interrupt Enable B 0 1 Interrupt r...

Page 892: ...g Clearing conditions When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFB after reading TGFB 1 Setting conditions When TCNT TGRB while TGRB is function...

Page 893: ...dividual port 1 pins P2DDR Port 2 Data Direction Register H FEB1 Port 2 7 P27DDR 0 W 6 P26DDR 0 W 5 P25DDR 0 W 4 P24DDR 0 W 3 P23DDR 0 W 0 P20DDR 0 W 2 P22DDR 0 W 1 P21DDR 0 W Specify input or output...

Page 894: ...A2DDR 0 W 1 PA1DDR 0 W Bit Initial value Read Write Specify input or output for individual port A pins PBDDR Port B Data Direction Register H FEBA Port B On chip ROM version Only 7 PB7DDR 0 W 6 PB6DDR...

Page 895: ...for individual port E pins Bit Initial value Read Write PFDDR Port F Data Direction Register H FEBE Port F 7 PF7DDR 1 W 0 W 6 PF6DDR 0 W 0 W 5 PF5DDR 0 W 0 W 4 PF4DDR 0 W 0 W 3 PF3DDR 0 W 0 W 0 PF0DDR...

Page 896: ...er I H FECC Interrupt Controller IPRJ Interrupt Priority Register J H FECD Interrupt Controller IPRK Interrupt Priority Register K H FECE Interrupt Controller 7 0 6 IPR6 1 R W 5 IPR5 1 R W 4 IPR4 1 R...

Page 897: ...designated for 16 bit access Area n is designated for 8 bit access n 7 to 0 Note Modes 6 and 7 are provided in the On chip ROM version only ASTCR Access State Control Register H FED1 Bus Controller 7...

Page 898: ...0 1 0 1 Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 0 1 0 1 0 1 Program wait not inserted 1 program wait state inserted 2 prog...

Page 899: ...0 1 0 1 Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 0 1 0 1 0 1 Program wait not inserted 1 program wait state inserted 2 prog...

Page 900: ...not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles Area 0 Burst ROM Enable 0 1 Area 0 is basi...

Page 901: ...ernal Addresses H 010000 to H 01FFFF 1 Enable Write Data Buffer Enable 0 1 WAIT Pin Enable 0 1 Wait input by WAIT pin disabled Wait input by WAIT pin enabled Write data buffer function not used Write...

Page 902: ...charge cycle is inserted Burst Access Enable 0 1 Burst disabled always full access RAS CS Down Mode 0 1 DRAM interface RAS up mode selected DRAM interface RAS down mode selected 2 CAS Method Select 0...

Page 903: ...pare Match Flag 0 1 Cleared by reading the CMF flag when CMF 1 then writing 0 to the CMF flag Clearing condition Setting condition Set when RTCNT RTCOR Compare Match Interrupt Enable 0 1 Interrupt req...

Page 904: ...0 3 RAMS 0 R W 0 RAM0 0 R W 2 RAM2 0 R W 1 RAM1 0 R W Bit Initial value Read Write RAM2 0 0 0 0 1 1 1 1 RAMS 0 1 1 1 1 1 1 1 1 RAM Select Flash Memory Area Select RAM1 0 0 1 1 0 0 1 1 RAM0 0 1 0 1 0...

Page 905: ...8 R W 17 R W Bit MAR0AH Initial value Read Write 19 R W 21 R W 22 R W 23 R W 24 0 25 0 26 0 27 0 28 0 29 0 30 0 31 0 0 R W 2 R W 1 R W 3 R W 4 R W 5 R W 6 R W 7 R W 8 R W 9 R W 10 R W 11 R W 12 R W 13...

Page 906: ...DMAC 16 R W 18 R W 17 R W 19 R W 21 R W 22 R W 23 R W 24 0 25 0 26 0 27 0 28 0 29 0 30 0 31 0 0 R W 2 R W 1 R W 3 R W 4 R W 5 R W 6 R W 7 R W 8 R W 9 R W 10 R W 11 R W 12 R W 13 R W 14 R W 15 R W 20...

Page 907: ...2 DMAC 16 R W 18 R W 17 R W 19 R W 21 R W 22 R W 23 R W 24 0 25 0 26 0 27 0 28 0 29 0 30 0 31 0 0 R W 2 R W 1 R W 3 R W 4 R W 5 R W 6 R W 7 R W 8 R W 9 R W 10 R W 11 R W 12 R W 13 R W 14 R W 15 R W 20...

Page 908: ...ister Block size counter Bit ETCR1A Initial value Read Write MAR1BH Memory Address Register 1BH H FEF8 DMAC MAR1BL Memory Address Register 1BL H FEFA DMAC 16 R W 18 R W 17 R W 19 R W 21 R W 22 R W 23...

Page 909: ...er destination address In full address mode Not used Bit IOAR1B Initial value Read Write ETCR1B Transfer Count Register 1B H FEFE DMAC 0 R W 2 R W 1 R W 3 R W 4 R W 5 R W 6 R W 7 R W 8 R W 9 R W 10 R...

Page 910: ...to all bits in DMACR0A and bits 8 4 and 0 in DMABCR are enabled Writes to all bits in DMACR0B bits 9 5 and 1 in DMABCR and bit 4 in DMATCR are disabled Writes to all bits in DMACR0B bits 9 5 and 1 in...

Page 911: ...C DMACR1B DMA Control Register 1B H FF05 DMAC 15 DTSZ 0 R W 14 SAID 0 R W 13 SAIDE 0 R W 12 BLKDIR 0 R W 11 BLKE 0 R W 8 0 R W 10 0 R W 9 0 R W 0 1 Byte size transfer Word size transfer Data Transfer...

Page 912: ...vated by SCI channel 1 reception data full interrupt Activated by TPU channel 0 compare match input capture A interrupt Activated by TPU channel 1 compare match input capture A interrupt Activated by...

Page 913: ...data empty interrupt Activated by SCI channel 0 reception data full interrupt Activated by SCI channel 0 transmission data empty interrupt Activated by A D converter conversion end interrupt 1 0 1 0...

Page 914: ...e Channel 0 Full Address Enable 0 Clearing of selected internal interrupt source at time of DMA transfer is disabled Channel 1 Data Transfer Acknowledge 1 Clearing of selected internal interrupt sourc...

Page 915: ...er Interrupt Enable A 7 DTME1 0 R W 6 DTE1 0 R W 5 DTME0 0 R W 4 DTE0 0 R W 3 DTIE1B 0 R W 0 DTIE0A 0 R W 2 DTIE1A 0 R W 1 DTIE0B 0 R W 0 1 Transfer suspended interrupt disabled Transfer suspended int...

Page 916: ...source at time of DMA transfer is disabled Channel 1B Data Transfer Acknowledge 1 Clearing of selected internal interrupt source at time of DMA transfer is enabled 0 Clearing of selected internal int...

Page 917: ...R W 4 DTE0A 0 R W 3 DTIE1B 0 R W 0 DTIE0A 0 R W 2 DTIE1A 0 R W 1 DTIE0B 0 R W Short address mode cont Bit DMABCRL Initial value Read Write Channel 0B Data Transfer Interrupt Enable 0 1 Transfer end in...

Page 918: ...0 R W 3 IRQ1SCB 0 R W 0 IRQ0SCA 0 R W 2 IRQ1SCA 0 R W 1 IRQ0SCB 0 R W IRQ7 to IRQ4 Sense Control IRQ3 to IRQ0 Sense Control 0 1 0 1 0 1 IRQn input low level Falling edge of IRQn input Rising edge of I...

Page 919: ...R W DTC Activation Enable Bit Initial value Read Write DTC activation by this interrupt is disabled Clearing conditions When the DISEL bit is 1 and data transfer has ended When the specified number o...

Page 920: ...be written after 1 is read Note DTC Software Activation Enable 0 1 DTC software activation is disabled Clearing condition When the DISEL bit is 0 and the specified number of transfers have not ended D...

Page 921: ...mode after execution of SLEEP instruction Standby Timer Select 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Standby time 8 192 states Standby time 16 384 states Standby time 32 768 states Standby time 65 536 states St...

Page 922: ...d Only 0 should be written to this bit Reserved Only 0 should be written to this bit Reserved for H8S 2398 H8S 2394 H8S 2392 and H8S 2390 Only 0 should be written to this bit Interrupt Control Mode Se...

Page 923: ...value Read Write Software Standby Mode Hardware Standby Mode Reserved for H8S 2398 H8S 2394 H8S 2392 and H8S 2390 Only 0 should be written to this bit Reserved Only 0 should be written to this bit MDC...

Page 924: ...enable Note SYSCR2 can only be accessed in the F ZTAT version In other versions this register cannot be written to and will return an undefined value if read Reserved Register H FF44 7 0 6 0 5 0 R W...

Page 925: ...match in TPU channel 2 Compare match in TPU channel 3 Output Trigger for Pulse Output Group 0 Bit Initial value Read Write Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match...

Page 926: ...1 in PODRH Pulse Output Group n Direct Inverted Output 0 1 Normal operation in pulse output group n output values updated at compare match A in the selected TPU channel Pulse Output Group n Normal Non...

Page 927: ...R W 2 NDER10 0 R W 1 NDER9 0 R W NDERH 7 NDER7 0 R W 6 NDER6 0 R W 5 NDER5 0 R W 4 NDER4 0 R W 3 NDER3 0 R W 0 NDER0 0 R W 2 NDER2 0 R W 1 NDER1 0 R W 0 1 Pulse outputs PO15 to PO8 are disabled Pulse...

Page 928: ...R W 3 POD11 0 R W 0 POD8 0 R W 2 POD10 0 R W 1 POD9 0 R W 7 POD7 0 R W 6 POD6 0 R W 5 POD5 0 R W 4 POD4 0 R W 3 POD3 0 R W 0 POD0 0 R W 2 POD2 0 R W 1 POD1 0 R W Note A bit that has been set for puls...

Page 929: ...b Address H FF4E 7 NDR15 0 R W 6 NDR14 0 R W 5 NDR13 0 R W 4 NDR12 0 R W 3 1 0 1 2 1 1 1 2 When pulse output group output triggers are different a Address H FF4C b Address H FF4E 7 1 6 1 5 1 4 1 3 ND...

Page 930: ...W 4 NDR4 0 R W 3 1 0 1 2 1 1 1 7 1 6 1 5 1 4 1 3 NDR3 0 R W 0 NDR0 0 R W 2 NDR2 0 R W 1 NDR1 0 R W Bit Initial value Read Write Bit Initial value Read Write Bit Initial value Read Write 1 When pulse o...

Page 931: ...R 0 P20 R 2 P22 R 1 P21 R State of port 2 pins Note Determined by the state of pins P27 to P20 Bit Initial value Read Write PORT3 Port 3 Register H FF52 Port 3 7 Undefined 6 Undefined 5 P35 R 4 P34 R...

Page 932: ...0 P60 R 2 P62 R 1 P61 R State of port 6 pins Note Determined by the state of pins P67 to P60 Bit Initial value Read Write PORTA Port A Register H FF59 Port A 7 PA7 R 6 PA6 R 5 PA5 R 4 PA4 R 3 PA3 R 0...

Page 933: ...PD6 R 5 PD5 R 4 PD4 R 3 PD3 R 0 PD0 R 2 PD2 R 1 PD1 R State of port D pins Note Determined by the state of pins PD7 to PD0 Bit Initial value Read Write PORTE Port E Register H FF5D Port E 7 PE7 R 6 P...

Page 934: ...R W 0 P10DR 0 R W 2 P12DR 0 R W 1 P11DR 0 R W Stores output data for port 1 pins P17 to P10 Bit Initial value Read Write P2DR Port 2 Data Register H FF61 Port 2 7 P27DR 0 R W 6 P26DR 0 R W 5 P25DR 0 R...

Page 935: ...0 R W 0 P60DR 0 R W 2 P62DR 0 R W 1 P61DR 0 R W Stores output data for port 6 pins P67 to P60 Bit Initial value Read Write PADR Port A Data Register H FF69 Port A 7 PA7DR 0 R W 6 PA6DR 0 R W 5 PA5DR...

Page 936: ...D3DR 0 R W 0 PD0DR 0 R W 2 PD2DR 0 R W 1 PD1DR 0 R W Stores output data for port D pins PD7 to PD0 Bit Initial value Read Write PEDR Port E Data Register H FF6D Port E 7 PE7DR 0 R W 6 PE6DR 0 R W 5 PE...

Page 937: ...and H8S 2390 Bit Initial value Read Write PBPCR Port B MOS Pull Up Control Register H FF71 Port B On chip ROM version Only 7 PB7PCR 0 R W 6 PB6PCR 0 R W 5 PB5PCR 0 R W 4 PB4PCR 0 R W 3 PB3PCR 0 R W 0...

Page 938: ...1 PE1PCR 0 R W Controls the MOS input pull up function incorporated into port E on a bit by bit basis Bit Initial value Read Write Note Setting is prohibited in the H8S 2352 H8S 2394 H8S 2392 and H8S...

Page 939: ...0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Parity Enable 0 1 Even parity Odd parity Parity Mode 0 1 0 1 0 1 clock 4 clock 16 clock 64 clock Clock Select 0 1...

Page 940: ...ND flag generated 11 0 etu after beginning of start bit Fixed high low level control possible set in SCR in addition to clock output on off control GSM Mode 0 1 Setting prohibited Parity bit addition...

Page 941: ...600H BRR0 Bit Rate Register 0 H FF79 SCI0 Smart Card Interface 0 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 0 1 R W 2 1 R W 1 1 R W Sets the serial transfer bit rate Note See section 14 2 8 Bit Rate Regi...

Page 942: ...t data empty interrupt TXI requests enabled Transmit Interrupt Enable Notes Bit Initial value Read Write Synchronous mode Internal clock SCK pin functions as serial clock output Asynchronous mode Inte...

Page 943: ...interrupt RXI request and receive error interrupt ERI request disabled Receive Interrupt Enable 0 1 Transmit data empty interrupt TXI requests disabled Transmit data empty interrupt TXI requests enabl...

Page 944: ...Setting conditions When the TE bit in SCR is 0 When TDRE 1 at transmission of the last bit of a 1 byte serial transmit character Clearing condition When 0 is written to PER after reading PER 1 Settin...

Page 945: ...ssion 1 0 etu after a 1 byte serial character is sent when GM 1 Clearing condition When 0 is written to PER after reading PER 1 Setting condition When in reception the number of 1 bits in the receive...

Page 946: ...1 1 0 1 TDR contents are transmitted LSB first Receive data is stored in RDR LSB first Smart Card Data Direction 0 1 TDR contents are transmitted as they are Receive data is stored in RDR as it is Sm...

Page 947: ...0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Parity Enable 0 1 Even parity Odd parity Parity Mode 0 1 0 1 0 1 clock 4 clock 16 clock 64 clock Clock Select 0 1...

Page 948: ...ND flag generated 11 0 etu after beginning of start bit Fixed high low level control possible set in SCR in addition to clock output on off control GSM Mode 0 1 Setting prohibited Parity bit addition...

Page 949: ...600H BRR1 Bit Rate Register 1 H FF81 SCI1 Smart Card Interface 1 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 0 1 R W 2 1 R W 1 1 R W Note See section 14 2 8 Bit Rate Register BRR for details Sets the seri...

Page 950: ...t data empty interrupt TXI requests enabled Transmit Interrupt Enable Notes Bit Initial value Read Write Synchronous mode Internal clock SCK pin functions as serial clock output Asynchronous mode Inte...

Page 951: ...interrupt RXI request and receive error interrupt ERI request disabled Receive Interrupt Enable 0 1 Transmit data empty interrupt TXI requests disabled Transmit data empty interrupt TXI requests enabl...

Page 952: ...e serial transmit character 1 Clearing condition When 0 is written to PER after reading PER 1 Setting condition When in reception the number of 1 bits in the receive data plus the parity bit does not...

Page 953: ...ion 1 0 etu after a 1 byte serial character is sent when GM 1 1 Clearing condition When 0 is written to PER after reading PER 1 Setting condition When in reception the number of 1 bits in the receive...

Page 954: ...1 1 0 1 TDR contents are transmitted LSB first Receive data is stored in RDR LSB first Smart Card Data Direction 0 TDR contents are transmitted as they are Receive data is stored in RDR as it is Smar...

Page 955: ...0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Parity Enable 0 1 Even parity Odd parity Parity Mode 0 1 0 1 0 1 clock 4 clock 16 clock 64 clock Clock Select 0 1...

Page 956: ...ND flag generated 11 0 etu after beginning of start bit Fixed high low level control possible set in SCR in addition to clock output on off control GSM Mode 0 1 Setting prohibited Parity bit addition...

Page 957: ...600H BRR2 Bit Rate Register 2 H FF89 SCI2 Smart Card Interface 2 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 0 1 R W 2 1 R W 1 1 R W Note See section 14 2 8 Bit Rate Register BRR for details Sets the seri...

Page 958: ...t data empty interrupt TXI requests enabled Transmit Interrupt Enable Notes Bit Initial value Read Write Synchronous mode Internal clock SCK pin functions as serial clock output Asynchronous mode Inte...

Page 959: ...interrupt RXI request and receive error interrupt ERI request disabled Receive Interrupt Enable 0 1 Transmit data empty interrupt TXI requests disabled Transmit data empty interrupt TXI requests enabl...

Page 960: ...e serial transmit character 1 Clearing condition When 0 is written to PER after reading PER 1 Setting condition When in reception the number of 1 bits in the receive data plus the parity bit does not...

Page 961: ...ion 1 0 etu after a 1 byte serial character is sent when GM 1 1 Clearing condition When 0 is written to PER after reading PER 1 Setting condition When in reception the number of 1 bits in the receive...

Page 962: ...1 1 0 1 TDR contents are transmitted LSB first Receive data is stored in RDR LSB first Smart Card Data Direction 0 TDR contents are transmitted as they are Receive data is stored in RDR as it is Smar...

Page 963: ...94 A D Converter ADDRCL A D Data Register CL H FF95 A D Converter ADDRDH A D Data Register DH H FF96 A D Converter ADDRDL A D Data Register DL H FF97 A D Converter 15 AD9 0 R 14 AD8 0 R 13 AD7 0 R 12...

Page 964: ...nabled A D Interrupt Enable 0 1 Single mode Scan mode Scan Mode 0 1 A D conversion stopped A D Start 0 A D End Flag CH1 0 1 0 1 CH0 0 1 0 1 0 1 0 1 Single Mode AN0 AN0 AN1 AN0 to AN2 AN0 to AN3 AN4 AN...

Page 965: ...are reserved so should always be written with 1 A D conversion start by external trigger is disabled A D conversion start by external trigger TPU is enabled A D conversion start by external trigger 8...

Page 966: ...rsion enabled Channel 0 and 1 D A conversion enabled Channel 0 and 1 D A conversion enabled Don t care 0 1 Analog output DA0 is disabled Channel 0 D A conversion is enabled D A Output Enable 0 0 1 Ana...

Page 967: ...k counted at falling edge 1 0 1 External clock counted at both rising and falling edges 1 Clock Select 0 1 CMFB interrupt requests CMIB are disabled CMFB interrupt requests CMIB are enabled Compare Ma...

Page 968: ...only 0 1 No change when compare match B occurs 0 is output when compare match B occurs 1 is output when compare match B occurs 0 1 0 1 Output Select Bit Initial value Read Write Bit Initial value Read...

Page 969: ...Constant Register B0 H FFB6 8 Bit Timer Channel 0 TCORB1 Time Constant Register B1 H FFB7 8 Bit Timer Channel 1 15 1 R W 14 1 R W 13 1 R W 12 1 R W 11 1 R W 10 1 R W 9 1 R W 8 1 R W 7 1 R W 6 1 R W 5...

Page 970: ...when OVF 1 then writing 0 to OVF 1 Overflow Flag 0 Interval timer mode Sends the CPU an interval timer interrupt request WOVI when TCNT overflows Watchdog timer mode Generates the WDTOVF signal 1 whe...

Page 971: ...verflow Flag Note Can only be written with 0 for flag clearing The method for writing to RSTCSR is different from that for general registers to prevent accidental overwriting For details see section 1...

Page 972: ...output level will be changed to the set initial output value Bit Initial value Read Write TSYR Timer Synchro Register H FFC1 TPU 7 0 6 0 5 SYNC5 0 R W 4 SYNC4 0 R W 3 SYNC3 0 R W 0 SYNC0 0 R W 2 SYNC2...

Page 973: ...tting condition FWE 1 and SWE 1 Erase Verify 0 1 Clears program mode Program mode is entered Setting condition FWE 1 SWE 1 and PSU 1 Program 0 1 Clears erase mode Erase mode is entered Setting conditi...

Page 974: ...tup 0 1 Clears erase setup Erase setup Setting condition FWE 1 and SWE 1 Erase Setup 0 1 Flash memory operates normally Writing erasing protect error protect to flash memory is disabled Clearing condi...

Page 975: ...B0 1 kbyte EB1 1 kbyte EB2 1 kbyte EB3 1 kbyte EB4 28 kbytes EB5 16 kbytes EB6 8 kbytes EB7 8 kbytes EB8 32 kbytes EB9 32 kbytes H 000000 to H 0003FF H 000400 to H 0007FF H 000800 to H 000BFF H 000C00...

Page 976: ...0 1 Clears erase mode Erase mode is entered Setting condition SWE 1 and ESU 1 Erase 1 0 1 Clears program verify mode Program verify mode is entered Setting condition SWE 1 Program Verify 1 0 1 Clears...

Page 977: ...to flash memory Writing erasing protect error protect to flash memory is enabled Setting condition See section 19 19 3 Error Protection Flash Memory Error Bit Initial value Read Write EBR1 Erase Block...

Page 978: ...on TCLKA pin input External clock counts on TCLKB pin input External clock counts on TCLKC pin input External clock counts on TCLKD pin input Time Prescaler 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Bit Initial va...

Page 979: ...l operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Mode 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Notes 1 2 MD3 is a reserved bit In a...

Page 980: ...e set to B 000 and 1 is used as the TCNT1 count clock this setting is invalid and input capture is not generated Bit Initial value Read Write Initial output is 0 output TGR0A is input capture register...

Page 981: ...perates as a buffer register Bit Initial value Read Write TGR0C is output compare register Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match 0 output a...

Page 982: ...V disabled Interrupt requests TCIV by TCFV enabled Overflow Interrupt Enable TGR Interrupt Enable D TGR Interrupt Enable C TGR Interrupt Enable B 0 1 Interrupt requests TGIA by TGFA bit disabled TGR I...

Page 983: ...ile DISEL bit of MRB in DTC is 0 When 0 is written to TGFB after reading TGFB 1 Setting conditions When TCNT TGRB while TGRB is functioning as output compare register When TCNT value is transferred to...

Page 984: ...W 5 0 R W 4 0 R W 3 0 R W 0 0 R W 2 0 R W 1 0 R W Up counter TGR0A Timer General Register 0A H FFD8 TPU0 TGR0B Timer General Register 0B H FFDA TPU0 TGR0C Timer General Register 0C H FFDC TPU0 TGR0D...

Page 985: ...clock counts on TCLKA pin input External clock counts on TCLKB pin input Internal clock counts on 256 Counts on TCNT2 overflow underflow Time Prescaler 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7 0 6 CCLR1 0 R W 5...

Page 986: ...ed PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Mode 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Note MD3 is a reserved bit In a write it should always...

Page 987: ...put capture at both edges Initial output is 0 output TGR1A is input capture register Output disabled Initial output is 1 output Capture input source is TIOCA1 pin Capture input source is TGR0A compare...

Page 988: ...Start Request Enable 0 1 Interrupt requests TCIU by TCFU disabled Interrupt requests TCIU by TCFU enabled Underflow Interrupt Enable TGR Interrupt Enable B 0 1 Interrupt requests TGIA by TGFA bit disa...

Page 989: ...r Clearing conditions When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFB after reading TGFB 1 Setting conditions When TCNT TGRB while TGRB is function...

Page 990: ...edges Internal clock counts on 1 Internal clock counts on 4 Internal clock counts on 16 Internal clock counts on 64 External clock counts on TCLKA pin input External clock counts on TCLKB pin input Ex...

Page 991: ...ed PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 Mode 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Note MD3 is a reserved bit In a write it should always...

Page 992: ...match Input capture at rising edge Input capture at falling edge Input capture at both edges Don t care Bit Initial value Read Write Output disabled Initial output is 0 output Output disabled Initial...

Page 993: ...Start Request Enable 0 1 Interrupt requests TCIU by TCFU disabled Interrupt requests TCIU by TCFU enabled Underflow Interrupt Enable TGR Interrupt Enable B 0 1 Interrupt requests TGIA by TGFA bit disa...

Page 994: ...rite Setting conditions When TCNT TGRA while TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture re...

Page 995: ...as an up down counter only in phase counting mode or when performing overflow underflow counting on another channel In other cases it functions as an up counter Up down counter Bit Initial value Read...

Page 996: ...1 Internal data bus PPG module DMA controller TPU module Pulse output enable DMA transfer acknowledge enable Pulse output DMA transfer acknowledge Output compare output PWM output enable Output compar...

Page 997: ...l data bus PPG module TPU module Pulse output enable Output compare output PWM output enable Output compare output PWM output Pulse output External clock input Input capture input WDDR1 WDR1 RDR1 RPOR...

Page 998: ...1 RPOR1 Internal data bus PPG module TPU module Pulse output enable Output compare output PWM output enable Output compare output PWM output Pulse output Input capture input WDDR1 WDR1 RDR1 RPOR1 n 4...

Page 999: ...C Q D P2n RDR2 RPOR2 Internal data bus PPG module TPU module Pulse output enable Output compare output PWM output enable Output compare output PWM output Pulse output Input capture input WDDR2 WDR2 RD...

Page 1000: ...s PPG module TPU module Pulse output enable Output compare output PWM output enable Counter external reset input Output compare output PWM output Pulse output 8 bit timer module Input capture input WD...

Page 1001: ...s PPG module TPU module Pulse output enable Output compare output PWM output enable Counter external reset input Output compare output PWM output Pulse output 8 bit timer module Input capture input WD...

Page 1002: ...module 8 bit timer TPU module Pulse output enable Compare match output enable Pulse output Compare match output Output compare output PWM output enable Output compare output PWM output Input capture i...

Page 1003: ...Internal data bus SCI module Serial transmit enable Serial transmit data WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 n 0 or 1 Notes 1 Output enable signal 2 Open drain control signal Write to P3DDR Write to P3...

Page 1004: ...bus SCI module Serial receive data enable Serial receive data WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 n 2 or 3 Notes 1 Output enable signal 2 Open drain control signal Write to P3DDR Write to P3DR Write to...

Page 1005: ...clock output enable Serial clock output Serial clock input enable Serial clock input WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 n 4 or 5 Notes 1 Output enable signal 2 Open drain control signal Write to P3DDR...

Page 1006: ...converter module Analog input RPOR4 n 0 to 5 Read port 4 Legend Figure C 4 a Port 4 Block Diagram Pins P40 to P45 P4n RPOR4 Internal data bus A D converter module Analog input D A converter module Ou...

Page 1007: ...am R P50DDR C Q D Reset WDDR0 Reset WDR5 R C Q D P50 RDR5 RPOR5 Internal data bus SCI module Serial transmit data output enable Serial transmit data WDDR5 WDR5 RDR5 RPOR5 Write to P5DDR Write to P5DR...

Page 1008: ...DDR C Q D Reset WDDR5 Reset WDR5 R C Q D P51 RDR5 RPOR5 Internal data bus SCI module Serial receive data enable Serial receive data WDDR5 WDR5 RDR5 RPOR5 Write to P5DDR Write to P5DR Read P5DR Read po...

Page 1009: ...Reset WDR5 R C Q D P52 Internal data bus SCI module Serial clock output enable Serial clock output Serial clock input enable Serial clock input WDDR5 WDR5 RDR5 RPOR5 Write to P5DDR Write to P5DR Read...

Page 1010: ...P53DDR C Q D Reset WDDR5 Reset WDR5 R C Q D P53 RDR5 RPOR5 Internal data bus A D converter A D converter external trigger input WDDR5 WDR5 RDR5 RPOR5 Legend Write to P5DDR Write to P5DR Read P5DR Rea...

Page 1011: ...P60DDR C Q D Reset WDDR6 Mode 7 Mode 4 5 6 Reset WDR6 R P60DR C Q D P60 RDR6 RPOR6 Internal data bus DMA controller Bus controller Chip select DMA request input WDDR6 WDR6 RDR6 RPOR6 Write to P6DDR Wr...

Page 1012: ...Mode 7 Mode 4 5 6 Reset WDR6 R P61DR C Q D P61 RDR6 RPOR6 Internal data bus Bus controller Chip select DMA controller DMA transfer end enable DMA transfer end WDDR6 WDR6 RDR6 RPOR6 Write to P6DDR Wri...

Page 1013: ...8 0600H R P62DDR C Q D Reset WDDR6 Reset WDR6 R P62DR C Q D P62 RDR6 RPOR6 Internal data bus DMA controller DMA request input WDDR6 WDR6 RDR6 RPOR6 Write to P6DDR Write to P6DR Read P6DR Read port 6 L...

Page 1014: ...3DDR C Q D Reset WDDR6 Reset WDR6 R C Q D P63 RDR6 RPOR6 Internal data bus DMA controller DMA transfer end enable DMA transfer end WDDR6 WDR6 RDR6 RPOR6 Write to P6DDR Write to P6DR Read P6DR Read por...

Page 1015: ...DDR C Q D Reset WDDR6 Reset WDR6 R P6nDR C Q D P6n RDR6 RPOR6 Internal data bus Interrupt controller IRQ interrupt input WDDR6 WDR6 RDR6 RPOR6 n 4 or 5 Write to P6DDR Write to P6DR Read P6DR Read port...

Page 1016: ...ode 7 Mode 4 5 6 Reset WDR6 R P6nDR C Q D P6n RDR6 RPOR6 Internal data bus Interrupt controller Bus controller Chip select IRQ interrupt input WDDR6 WDR6 RDR6 RPOR6 n 6 or 7 Write to P6DDR Write to P6...

Page 1017: ...ress bus WDDRA WDRA WODRA WPCRA RDRA RPORA RODRA RPCRA n 0 to 3 Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR PAnDR Reset WDDRA R Mode 4 5 C Q...

Page 1018: ...WPCRA RDRA RPORA RODRA RPCRA Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR PA4DR Reset WDDRA R Mode 4 5 C Q D PA4DDR Reset WODRA RPCRA R C Q D...

Page 1019: ...RA RDRA RPORA RODRA RPCRA n 5 to 7 Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR PAnDR WDDRA C Q D PAnDDR Reset WODRA RPCRA R C Q D PAnODR 1 2...

Page 1020: ...et WDRB R C Q D PBn RDRB RPORB Internal data bus Internal address bus WDDRB WDRB WPCRB RDRB RPORB RPCRB n 0 to 7 Write to PBDDR Write to PBDR Write to PBPCR Read PBDR Read port B Read PBPCR PBnDR Rese...

Page 1021: ...et WDRC R C Q D PCn RDRC RPORC PCnDR Reset WDDRC R Mode 4 5 C Q D PCnDDR RPCRC Mode 7 Mode 4 5 6 Internal data bus Internal address bus WDDRC WDRC WPCRC RDRC RPORC RPCRC n 0 to 7 Write to PCDDR Write...

Page 1022: ...s External address upper write WDDRD WDRD WPCRD RDRD RPORD RPCRD n 0 to 7 Write to PDDDR Write to PDDR Write to PDPCR Read PDDR Read port D Read PDPCR PDnDR WDDRD C Q D PDnDDR RPCRD Mode 7 Mode 4 5 6...

Page 1023: ...RPCRE Reset R Internal upper data bus Internal lower data bus Mode 7 Mode 4 5 6 External address lower read WDDRE WDRE WPCRE RDRE RPORE RPCRE n 0 to 7 Write to PEDDR Write to PEDR Write to PEPCR Read...

Page 1024: ...k Diagram R PF0DDR C Q D Reset WDDRF Reset WDRF R C Q D PF0 RDRF RPORF Internal data bus Bus request input WDDRF WDRF RDRF RPORF Write to PFDDR Write to PFDR Read PFDR Read port F PF0DR Bus controller...

Page 1025: ...Q D Reset WDDRF Mode 4 5 6 Reset WDRF R PF1DR C Q D PF1 RDRF RPORF Internal data bus Bus controller BRLE output Bus request acknowledge output WDDRF WDRF RDRF RPORF Write to PFDDR Write to PFDR Read P...

Page 1026: ...eset WDRF R PF2DR C Q D PF2 RDRF RPORF Internal data bus Bus request output enable Bus request output Wait input LCAS output LCAS output enable WDDRF WDRF RDRF RPORF Write to PFDDR Write to PFDR Read...

Page 1027: ...3DDR C Q D Reset WDDRF Mode 4 5 6 Reset WDRF R PF3DR C Q D PF3 RDRF RPORF Internal data bus Bus controller LWR output WDDRF WDRF RDRF RPORF Write to PFDDR Write to PFDR Read PFDR Read port F Mode 7 Mo...

Page 1028: ...F4DDR C Q D Reset WDDRF Reset WDRF R PF4DR C Q D PF4 RDRF RPORF Internal data bus Bus controller HWR output WDDRF WDRF RDRF RPORF Write to PFDDR Write to PFDR Read PFDR Read port F Legend Mode 4 5 6 M...

Page 1029: ...F5DDR C Q D Reset WDDRF Reset WDRF R PF5DR C Q D PF5 RDRF RPORF Internal data bus Bus controller RD output WDDRF WDRF RDRF RPORF Write to PFDDR Write to PFDR Read PFDR Read port F Legend Mode 4 5 6 Mo...

Page 1030: ...F6DDR C Q D Reset WDDRF Reset WDRF R PF6DR C Q D PF6 RDRF RPORF Internal data bus Bus controller AS output WDDRF WDRF RDRF RPORF Write to PFDDR Write to PFDR Read PFDR Read port F Legend Mode 4 5 6 Mo...

Page 1031: ...38 0600H WDDRF Reset WDRF R PF7DR C Q D PF7 RDRF RPORF Internal data bus WDDRF WDRF RDRF RPORF Note Set priority Reset R Mode 4 5 6 S C Q PF7DDR Write to PFDDR Write to PFDR Read PFDR Read port F D Le...

Page 1032: ...lock Diagram R PG0DDR C Q D Reset WDDRG Mode 4 5 6 Reset WDRG R PG0DR C Q D PG0 RDRG RPORG Internal data bus Bus controller CAS enable CAS output WDDRG WDRG RDRG RPORG Write to PGDDR Write to PGDR Rea...

Page 1033: ...R C Q D Reset WDDRG Reset WDRG R PGnDR C Q D PGn RDRG RPORG Internal data bus Bus controller Chip select WDDRG WDRG RDRG RPORG n 1 to 3 Write to PGDDR Write to PGDR Read PGDR Read port G Mode 7 Mode 4...

Page 1034: ...set WDRG R PG4DR C Q D PG4 RDRG RPORG Internal data bus Bus controller Chip select WDDRG WDRG RDRG RPORG Write to PGDDR Write to PGDR Read PGDR Read port G Mode 7 Mode 6 7 Mode 4 5 Mode 4 5 6 Reset R...

Page 1035: ...7 T T T DAOE0 1 kept DAOE0 0 T kept I O port P45 to P40 4 to 7 T T T T T Input port Port 5 4 to 7 T kept T kept kept I O port P65 to P62 4 to 7 T kept T kept kept I O port P67 CS7 P66 CS6 P61 CS5 P60...

Page 1036: ...ept T DDR OPE 0 T DDR OPE 1 kept T DDR 0 Input port DDR 1 Address output 7 T kept T kept kept I O port Port D 4 to 6 T T 1 T T T Data bus 7 T kept T kept kept I O port Port E 4 to 6 8 bit bus T kept T...

Page 1037: ...CK T BRLE 0 kept BRLE 1 H L BRLE 0 I O port BRLE 1 BACK 7 T kept T kept kept I O port PF0 BREQ 4 to 6 T BRLE 0 kept BRLE 1 BREQ T BRLE 0 kept BRLE 1 T T BRLE 0 I O port BRLE 1 BREQ PG4 CS0 4 5 H DDR 0...

Page 1038: ...1016 REJ09B0138 0600H BREQOE BREQO pin enable DRAME DRAM space setting LCASE DRAM space setting CW2 LCASS 0 Notes 1 Indicates the state after completion of the executing bus cycle 2 Manual reset is on...

Page 1039: ...oes to the power on reset state 2 after a high level is detected at the NMI pin While the chip detects a low level at the NMI pin the manual reset state 1 is established The pin states are indetermina...

Page 1040: ...During this interval the pins are in the high impedance state After detecting a high level at the STBY pin the chip starts oscillation Note Excerpt for the H8S 2357 ZTAT all resets are power on reset...

Page 1041: ...BY signal goes low delay from STBY low to RES high 0 ns or more STBY RES t2 0 ns t1 10 tcyc Figure F 1 Timing of Transition to Hardware Standby Mode 2 To retain RAM contents with the RAME bit cleared...

Page 1042: ...TQFP TFP 120 HD6412352F 128 pin QFP FP 128B Table G 2 H8S 2398 H8S 2394 H8S 2392 H8S 2390 Group Product Code Lineup Product Type Product Code Mark Code Package Hitachi Package Code H8S 2398 Masked ROM...

Page 1043: ...10 0 5 0 1 16 0 0 2 0 4 0 10 0 10 1 20 Max 0 17 0 05 0 8 90 61 1 30 91 120 31 60 M 0 17 0 05 1 0 1 00 1 2 0 15 0 04 0 15 0 04 As of January 2003 Unit mm Figure H 1 TFP 120 Package Dimension Package Co...

Page 1044: ...Rev 6 00 Oct 28 2004 page 1016 of 1016 REJ09B0138 0600H...

Page 1045: ...TAT TM Publication Date 1st Edition November 1997 Rev 6 00 October 28 2004 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Technical Documentation Information Department Re...

Page 1046: ...1628 585 100 Fax 44 1628 585 900 Renesas Technology Hong Kong Ltd 7th Floor North Tower World Finance Centre Harbour City 1 Canton Road Tsimshatsui Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2730 607...

Page 1047: ...H8S 2357 Group H8S 2357F ZTATTM H8S 2398F ZTATTM Hardware Manual 2 6 2 Ote machi Chiyoda ku Tokyo 100 0004 Japan...

Reviews:

No comments

Related manuals for ZTAT H8S/2357F

Brand: Baicells Pages: 8

Brand: IBM Pages: 104

System Storage TS3100

Brand: IBM Pages: 375

Brand: Garland Pages: 6

Brand: protech Pages: 95

Brand: C&T Solution Pages: 129

UniFi WiFi BaseStation XG

Brand: Ubiquiti Pages: 19

Emotron OSTO 100

Brand: CG Pages: 112

Brand: Idis Pages: 22

NVR41-4KS2 Series

Brand: Dahua Pages: 452

Brand: Gearlinx Pages: 23

Brand: IBM Pages: 130

MTDOT-868 Series

Brand: Multitech Pages: 60

ROADRECORDER 8400 NVR

Brand: Safety Vision Pages: 27

Gen3 Ethernet Module

Brand: NCD Pages: 18

Brand: ZALMAN Pages: 12

Brand: Martin Pages: 41

TeleLite 720920 Series

Brand: Positron Pages: 21

Brands by name

0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Popular brands

Load more brands