Renesas ZTAT H8S/2357F, Hardware Manual

Page: 970 / 1047

Rev.6.00 Oct.28.2004 page 942 of 1016
REJ09B0138-0600H
TCSR—Timer Control/Status Register H'FFBC (W), H'FFBC (R) WDT
The method for writing to TCSR is different from that for general registers to prevent accidental
overwriting. For details see section 13.2.4, Notes on Register Access.
Note: * Can only be written with 0 for flag clearing.
Notes: 1. The
WDTOVF
pin function is not available in the
F-ZTAT version, H8S/2398, H8S/2394, H8S/2392, or
H8S/2390.
2. For details of the case where TCNT overflows in
watchdog time mode, see section 13.2.3, Reset
Control/Status Register(RSTCSR).
0 [Clearing condition]
Cleared by reading TCSR when OVF = 1, then writing 0 to OVF
1
Overflow Flag
0 Interval timer mode: Sends the CPU an interval timer interrupt
request (WOVI) when TCNT overflows
Watchdog timer mode: Generates the WDTOVF signal
*
1
when
TCNT overflows
*
2
1
Timer Mode Select
0
1
TCNT is initialized to H'00 and halted
TCNT counts
Timer Enable
Clock Select
CKS2 CKS1 CKS0 Clock
Overflow period *
(when ø = 20 MHz)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ø/2 (initial value)
ø/64
ø/128
ø/512
ø/2,048
ø/8,192
ø/32,768
ø/131,072
25.6
µ
s
819.2
µ
s
1.6ms
6.6ms
26.2ms
104.9ms
419.4ms
1.68s
Note:
*
The overflow period is the time from when TCNT
starts counting up from H'00 until overflow occurs.
[Setting condition]
Set when TCNT overflows from H'FF to H'00 in interval timer mode
7
OVF
0
R/(W)
*
6
WT/IT
0
R/W
5
TME
0
R/W
4
—
1
—
3
—
1
—
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Bit
Initial value
Read/Write
:
:
: