Renesas ZTAT H8S/2357F, Hardware Manual

Page: 279 / 1047

Rev.6.00 Oct.28.2004 page 251 of 1016
REJ09B0138-0600H
8.3.2 Activation Sources
The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be
directed to the CPU or DTC, as designated by the corresponding DTCER bit. An interrupt becomes a DTC activation
source when the corresponding bit is set to 1, and a CPU interrupt source when the bit is cleared to 0.
At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or
corresponding DTCER bit is cleared. Table 8-3 shows activation source and DTCER clearance. The activation source flag,
in the case of RXI0, for example, is the RDRF flag of SCI0.
Table 8-3 Activation Source and DTCER Clearance
Activation Source
When the DISEL Bit Is 0 and
the Specified Number of
Transfers Have Not Ended When the DISEL Bit Is 1, or when
the Specified Number of Transfers
Have Ended
Software activation The SWDTE bit is cleared to 0 The SWDTE bit remains set to 1
An interrupt is issued to the CPU
Interrupt activation The corresponding DTCER bit
remains set to 1
The activation source flag is
cleared to 0
The corresponding DTCER bit is cleared
to 0
The activation source flag remains set to 1
A request is issued to the CPU for the
activation source interrupt
Figure 8-3 shows a block diagram of activation source control. For details see section 5, Interrupt Controller.
On-chip
supporting
module
IRQ interrupt
DTVECR
Selection circuit
Interrupt controller
CPU
DTC
DTCER
Clear
controller
Select
Interrupt
request
Source flag cleared
Clear
Clear request
Interrupt mask
Figure 8-3 Block Diagram of DTC Activation Source Control
When an interrupt has been designated a DTC activation source, existing CPU mask level and interrupt controller
priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with
the default priorities.