Intel 6300ESB ICH, Design Manual

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January 2007 47
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Intel
®
Pentium
®
M/Celeron
®
M Processor FSB Design and Power Delivery Guidelines
Skew minimization requires pin-to-pad trace length matching of the Intel Pentium M/Celeron M
Processor FSB source synchronous signals that belong to the same group including the strobe
signals of that group. Refer to
Section 4.1.2.1 for trace length matching and package
compensations requirements.
Current simulation results provide routing guidelines using 3:1 spacing for the Intel Pentium
M/Celeron M Processor FSB source synchronous data and strobe signals. This implies a minimum
of 12 mil spacing (i.e., 16 mil minimum pitch) for a 4 mil trace width. Practical cases of escape
routing under the GMCH or Intel Pentium M/Celeron M Processor package outline and vicinity
may not even allow the implementation of 2:1 trace spacing requirements. Although every attempt
shall be made to maximize the signal spacing in these areas, it is allowable to have 1:1 trace
spacing underneath the GMCH and the Intel Pentium M/Celeron M Processor package outlines and
up to 200 – 300 mils outside the package outline. The benefits of additional spacing include
increased signal quality and voltage margining. The trace routing and length matching
requirements are as follows in
Section 4.1.3.1 to Section 4.1.3.3 .
4.1.3.1 Source Synchronous – Data Group
Robust operation of the 400 MHz, source synchronous data signals require tight skew control. For
this reason, these signals are split into matched groups as outlined in
Table 5 . All the signals within
the same group shall be kept on the same layer of motherboard routing and shall be routed to the
same pad-to-pin length within ±100 mils of the associated strobes. Only the Intel Pentium
M/Celeron M Processor has the package trace equalization for signals within each data and address
group. The GMCH does not have package trace equalization for signals within each data and
address group. All signals shall be routed on the system board to meet the pad-to-pin matching
requirement of ± 100 mils. Refer to
Table 9 for the Intel 855GME chipset package lengths.
Figure 13. Layer 3 Intel
®
Pentium
®
M/Celeron
®
M Processor FSB Source Synchronous
Address Signals
Layer 3
FSB Address