Design Guide
173
Intel
®
855GME Chipset and Intel
®
82801DB ICH4 Embedded Platform Design Guide
AGP Port Design Guidelines
AGP Port Design Guidelines
7
For detailed AGP interface functionality (e.g., protocols, rules, signaling mechanisms), refer to the
latest AGP Interface Specification, Revision 2.0, which can be found at
.
7.1
AGP Interface
The 855GME AGP buffers operate in only one mode: 1.5-V drive, not 3.3-V safe. This mode is
compliant with the AGP 2.0 Specification.
AGP 4X, 2X and 1X must operate at 1.5 V. The AGP interface supports up to 4X AGP signaling.
AGP semantic cycles to DRAM are not snooped on the host bus.
The GMCH supports PIPE# or SBA [7:0] AGP address mechanisms, but not both simultaneously.
Either the PIPE# or the SBA [7:0] mechanism must be selected during system initialization.
The AGP interface is clocked from a 66-MHz clock. The AGP interface is asynchronous to the host
bus, system memory, and internal graphics device. When AGP interface has been enabled, the
internal graphics will be disabled using GMCH strapping option. The AGP interface is
synchronous to the hub interface with a clock ratio of 1:1 (66 MHz: 66 MHz).
The GMCH multiplexes the AGP signal interface with two DVO ports. These DVO ports are
capable of supporting a variety of digital display devices such as TMDS transmitters and TV-Out
encoders. It is possible to use the DVO ports in dual-channel mode to support higher resolutions
and refresh rates (single channel mode is limited to a 165-MHz pixel clock rate).
7.1.1
AGP 2.0
The AGP Interface Specification, Revision 2.0, enhances the functionality of the original AGP
Interface Specification, Revision 1.0, by allowing 4X data transfers (i.e., four data samples per
clock), and 1.5-volt operation. The 4X operation of the AGP interface provides for "quad-
pumping" of the AGP AD (address/data) and SBA (side-band addressing) buses. That is, data is
sampled four times during each 66-MHz AGP clock. This means that each data cycle is ¼ of a 15-
ns (66-MHz) clock or 3.75 ns. It is important to understand that 3.75 ns is the data cycle time, not
the clock cycle time. During 2X operation, data is sampled twice during a 66-MHz clock cycle.
Therefore, the data cycle time is 7.5 ns. To allow for these high-speed data transfers, the 2X mode
of AGP operation uses source-synchronous data strobing. During 4X operation, the AGP interface
uses differential source-synchronous strobing.
With data cycle times as small as 3.75 ns and setup/hold times of one ns, propagation delay
mismatch is critical. In addition to reducing propagation delay mismatch, it is important to
minimize noise. Noise on the data lines will cause the settling time to be long. If the mismatch
between a data line and the associated strobe is too great, or if there is noise on the interface,
incorrect data will be sampled. The low-voltage operation on AGP (1.5 V) requires even more
noise immunity.
Summary of Contents for 6300ESB ICH
Page 24: ...24 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Introduction...
Page 102: ...102 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide...
Page 122: ...122 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide...
Page 190: ...190 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Hub Interface...
Page 318: ...318 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist...
