Intel 6300ESB ICH, Design Manual

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Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Intel
®
Pentium
®
M/Celeron
®
M Processor FSB Design and Power Delivery Guidelines
Figure 7 depicts the common clock topology.
4.1.3 Source Synchronous Signals General Routing Guidelines
All source synchronous signals use an AGTL+ bus driver technology with on-die GTL termination
resistors connected in a point-to-point, Zo = 55
Ω
controlled impedance topology between the Intel
Pentium M/Celeron M Processor and the GMCH. No external termination is needed on these
signals. Source synchronous Intel Pentium M/Celeron M Processor FSB address signals operate at
a double-pumped rate of 200 MHz while the source synchronous processor FSB data signals
operate at a quad-pumped rate of 400 MHz. High speed operation of the source synchronous
signals requires careful attention to their routing considerations. The following guidelines shall be
strictly adhered to, to ensure robust high-frequency operation of these signals.
Figure 7. Common Clock Topology
Table 4. Intel
®
Pentium
®
M/Celeron
®
M Processor and Intel
®
GMCH FSB Common Clock
Signal Package Lengths and Minimum Board Trace Lengths
Signal Names Package Length
Total Pad-to-Pad Min.
Length Requirements L1
Minimum
Routable Board
Trace Length CPU GMCH CPU GMCH
ADS# ADS# 454 761 2212 997
BNR# BNR# 506 408 2212 1298
BPRI# BPRI# 424 573 2212 1215
BR0# BR0# 336 465 2212 1411
DBSY# DBSY# 445 608 2212 1159
DEFER# DEFER# 349 572 2212 1291
DPWR# DPWR# 506 518 2212 1188
DRDY# DRDY# 529 347 2212 1336
HIT# HIT# 420 489 2212 1303
HITM# HITM# 368 641 2212 1203
LOCK# HLOCK# 499 515 2212 1198
RS0# RS0# 576 321 2212 1315
RS1# RS1# 524 495 2212 1193
RS2# RS2# 451 514 2212 1247
TRDY# HTRDY# 389 511 2212 1312
RESET# CPURESET# 455 656 2212 1101
GMCH Processor
Length L1
Package trace
Motherboard PCB trace
Pad Pad