January 2007
301
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Layout Checklist
6300ESB Interface Signals
IERR#
•
May be routed as a test point or to any
optional system receiver.
•
May be routed as strip-line or micro-strip with
trace impedance = 55
Ω
± 15%.
•
Place series resistor R1 within 3 inches of
system receiver.
•
Place pull-up resistor Rtt within 3 inches of
series resistor R1.
•
Pull-up voltage for termination resistor Rtt is
VCCP (1.05).
•
Asynchronous AGTL+ Output
Signal.
•
Refer to Topology 1A in
for resistor values
and trace length
recommendations.
PROCHOT#
•
May be routed as strip-line or micro-strip with
trace impedance = 55
Ω
± 15%.
•
Use recommended voltage translation logic
for an appropriate system receiver.
•
Pull-up voltage for termination resistor Rtt is
VCCP (1.05)
•
Place series resistor Rs at the beginning of
trace T-split and within 3 inches from Q1.
•
Asynchronous AGTL+ Output
Signal.
•
Refer to Topology 1C in
for resistor values
and trace length
recommendations.
FERR#
THERMTRIP#
•
Connect FERR# to the processor and the
Intel
®
6300ESB.
•
Recommend connecting processor signal
THERMTRIP# to the 6300ESB, but may be
connected to any optional system receiver,
with consideration for any voltage level
translation if necessary.
•
May be routed as strip-line or micro-strip with
trace impedance = 55
Ω
± 15%.
•
Place series resistor R1 within 3 inches of
system receiver.
•
Place pull-up resistor Rtt within 3 inches of
series resistor R1.
•
Pull-up voltage for termination resistor Rtt is
VCCP (1.05).
•
Asynchronous AGTL+ Output
Signals.
•
Refer to Topology 1B in
for resistor values
and trace length
recommendations.
•
Refer to
for
voltage translation
recommendations.
IPWRGOOD
•
May be routed as strip-line or micro-strip with
trace impedance = 55
Ω
± 15%
•
Route point-to-point between an AND gate
output (AND of PWRGD_3V and
CPU_VR_PWRGD) signal and CPU signal
PWRGOOD, trace length range between 0.5
and 12 inches.
•
Place a termination resistor Rtt within 3
inches of CPU pin. T-split routing should not
be used.
•
Pull-up voltage for termination resistor Rtt is
VCCP (1.05)
•
Asynchronous Open Drain CMOS
Input Signal.
•
Refer to Topology 2A in
for resistor values
and detailed routing
recommendations.
Table 148. Processor Layout Checklist (Sheet 2 of 7)
Checklist Items
Recommendations
Comments
Summary of Contents for 6300ESB ICH
Page 24: ...24 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Introduction...
Page 102: ...102 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide...
Page 122: ...122 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide...
Page 190: ...190 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Hub Interface...
Page 318: ...318 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist...
