Intel 6300ESB ICH Design Manual Download Page 7

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Intel

855GME Chipset and Intel

6300ESB ICH Embedded Platform Design Guide

6.4.1

DVOB and DVOC Module Design .......................................................................168
6.4.1.1

Generic Connector Model .................................................................... 169

6.5

DVO GMBUS and DDC Interface Considerations ............................................................ 170
6.5.1

Leaving the GMCH DVOB or DVOC Port Unconnected......................................171

6.6

Miscellaneous Input Signals and Voltage Reference ....................................................... 171

AGP Port Design Guidelines .................................................................................................... 173

7.1

AGP Interface ................................................................................................................... 173
7.1.1

AGP 2.0 ............................................................................................................... 173

7.1.2

AGP Interface Signal Groups .............................................................................. 174

7.2

AGP Routing Guidelines ................................................................................................... 175
7.2.1

1x Timing Domain Routing Guidelines................................................................. 175
7.2.1.1

Trace Length Requirements for AGP 1X .............................................175

7.2.1.2

Trace Spacing Requirements .............................................................. 175

7.2.1.3

Trace Length Mismatch .......................................................................175

7.2.2

2x/4x Timing Domain Routing Guidelines............................................................ 175
7.2.2.1

Trace Length Requirements for AGP 2X/4X ........................................ 175

7.2.2.2

Trace Spacing Requirements .............................................................. 176

7.2.2.3

Trace Length Mismatch Requirements ................................................ 177

7.2.3

AGP Clock Skew ................................................................................................. 177

7.2.4

AGP Signal Noise Decoupling Guidelines ........................................................... 178

7.2.5

AGP Interface Package Lengths ......................................................................... 178

7.2.6

AGP Routing Ground Reference ......................................................................... 179

7.2.7

Pull-Ups ............................................................................................................... 180

7.2.8

AGP VDDQ and VCC ..........................................................................................181

7.2.9

VREF Generation for AGP 2.0 (2X and 4X) ........................................................ 181
7.2.9.1

1.5 V AGP Interface (2X/4X) ................................................................181

7.2.10 AGP Compensation ............................................................................................. 181
7.2.11 PM_SUS_CLK/AGP_PIPE# Design Consideration .............................................181

Hub Interface.............................................................................................................................. 183

8.1

8-Bit Hub Interface Routing Guidelines. ........................................................................... 183
8.1.1

8-Bit Hub Interface Data Signals ......................................................................... 183

8.1.2

8-Bit Hub Interface Signal Referencing ............................................................... 184

8.1.3

8-Bit Hub Interface Strobe Signals ...................................................................... 184

8.1.4

8-bit Hub Interface HIREF and HI_VSWING Generation/Distribution.................. 184
8.1.4.1

GMCH Single Generated Voltage Reference Divider Circuit ............... 187

8.1.4.2

Separate GMCH Voltage Divider Circuits for HLVREF and PSWING . 188

8.1.5

Hub Interface Compensation ............................................................................... 189

8.1.6

8-Bit Hub Interface Decoupling Guidelines .......................................................... 189

8.1.7

Terminating HI_11 If Not Used ............................................................................189

Intel

6300ESB Design Guidelines ..........................................................................................191

9.1

Serial ATA Interface.......................................................................................................... 191
9.1.1

Layout Guidelines ................................................................................................ 191
9.1.1.1

General Routing and Placement .......................................................... 191

9.1.1.2

Serial ATA Trace Separation ............................................................... 191

9.1.1.3

Serial ATA Trace Length Pair Matching............................................... 192

9.1.1.4

Serial ATA Trace Length Guidelines.................................................... 192

9.1.1.5

SATA BIAS Connections .....................................................................192

9.1.1.6

SATALED# Implementation ................................................................. 193

Summary of Contents for 6300ESB ICH

Page 1: ...et and Intel 6300ESB ICH Embedded Platform For use with the Intel Pentium M Processor Intel Pentium M Processor on 90 nm process with 2 MB L2 cache and the Intel Celeron M Processor Design Guide Octob...

Page 2: ...lished specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your produc...

Page 3: ...k Up 33 3 2 Alternate Stack Ups 35 4 Intel Pentium M Celeron M Processor FSB Design and Power Delivery Guidelines 37 4 1 Intel Pentium M Celeron M Processor FSB Design Recommendations 37 4 1 1 Recomme...

Page 4: ...ocessors on 90 nm process with 2 MB L2 Cache 74 4 2 Intel System Validation Debug Support 75 4 2 1 ITP Support 75 4 2 1 1 Background Justification 75 4 2 1 2 Implementation 75 4 2 2 Pentium M Celeron...

Page 5: ...V Power Delivery Guidelines 110 4 8 2 2 GMCH and DDR SMVREF Design Recommendations 111 4 8 2 3 DDR SMRCOMP Resistive Compensation 111 4 8 2 4 DDR VTT Termination 112 4 8 2 5 DDR SMRCOMP and VTT 1 25...

Page 6: ...5 4 7 3 CPC to Clock Length Matching Requirements 148 5 4 7 4 CPC Group Package Length Table 150 5 4 8 Feedback RCVENOUT RCVENIN 150 5 5 ECC Guidelines 150 5 5 1 GMCH ECC Functionality 150 5 5 2 DRAM...

Page 7: ...GP Routing Ground Reference 179 7 2 7 Pull Ups 180 7 2 8 AGP VDDQ and VCC 181 7 2 9 VREF Generation for AGP 2 0 2X and 4X 181 7 2 9 1 1 5 V AGP Interface 2X 4X 181 7 2 10 AGP Compensation 181 7 2 11 P...

Page 8: ...3 USB BIAS Connections 211 9 6 1 4 USB 2 0 Termination 212 9 6 1 5 USB 2 0 Trace Length Pair Matching 212 9 6 1 6 USB 2 0 Trace Length Guidelines 212 9 6 2 Plane Splits Voids and Cut Outs Anti Etch 2...

Page 9: ...ling 240 9 13 3 In circuit FWH Programming 240 9 13 4 FWH INIT Voltage Compatibility 240 9 13 5 FWH VPP Design Guidelines 241 9 14 GPIO Summary 242 9 15 Power Management 244 9 15 1 SYS_RESET Usage Mod...

Page 10: ...Analog Converter DAC Checklist 280 12 3 5 Miscellaneous Signal Checklist 281 12 3 5 1 Intel Pentium M Celeron M Processor GST 2 0 Configurations 281 12 3 6 GMCH Decoupling Recommendations Checklist 2...

Page 11: ...Embedded Platform Design Guide 13 3 5 AC 97 Layout Checklist 315 13 3 5 1 RTC Layout Checklist 315 13 3 6 PCI X Layout Checklist 316 13 3 7 PCI Layout Checklist 316 13 3 8 FWH Decoupling Layout Check...

Page 12: ...ration for Topology 1A 59 17 Routing Illustration for Topology 1B 60 18 Routing Illustration for Topology 1C 61 19 Routing Illustration for Topology 2A 61 20 Routing Illustration for Topology 2B 62 21...

Page 13: ...VREF 2 0 Reference Voltage Generation Circuit 113 56 GMCH HAVREF Reference Voltage Generation Circuit 113 57 GMCH HCCVREF Reference Voltage Generation Circuit 114 58 Primary Side of the Motherboard La...

Page 14: ...Interface 207 105 Motherboard AC 97 CNR Implementation with a Single Codec Down On Board 208 106 Motherboard AC 97 CNR Implementation without Codec Down On Board 209 107 Trace Routing 211 108 Recomme...

Page 15: ...y 255 141 PCI Clock Group Topology 256 142 CLK14 Clock Group Topology 257 143 DOTCLK Clock Topology 258 144 SSCCLK Clock Topology 259 145 USBCLK Clock Topology 260 146 Source Shunt Termination 261 147...

Page 16: ...1C 61 14 Layout Recommendations for Topology 2A 62 15 Layout Recommendations for Topology 2B 62 16 Layout Recommendations for Topology 3 63 17 Processor RESET Signal Routing Guidelines with ITP700FLE...

Page 17: ...up Resistor Values 181 66 Hub Interface 1 5 Data Signals Routing Summary 183 67 Hub Interface 1 5 Strobe Signals Routing Summary 184 68 8 Bit Hub Interface HIREF HI_VSWING Generation Circuit Specific...

Page 18: ...straints 257 111 DOTCLK Clock Routing Constraints 258 112 SSCCLK Clock Routing Constraints 259 113 USBCLK Clock Routing Constraints 260 114 SCR SCR Routing Guidelines 261 115 Connection Recommendation...

Page 19: ...48 Processor Layout Checklist 300 149 Intel 855GME Chipset GMCH Layout Checklist 307 150 8 Bit Hub Interface Layout Checklist 312 151 Serial ATA Interface Layout Checklist 313 152 IDE Interface Layout...

Page 20: ...replace with AND gate Figure will be updated as well changed reference to 6300ESB in schematics checklist and layout checklist to AND gate Deleted duplicate copy of lntel 6300ESB power delivery figur...

Page 21: ...chronous Pentium M Celeron M processor system bus using a split transaction deferred reply protocol Table 1 presents conventions and terminology used in this document Note Unless otherwise noted all d...

Page 22: ...em Codec PCI Peripheral Component Interconnect PCM Pulse Code Modulation PLC Platform LAN Connect RTC Real Time Clock SATA Serial Advanced Technology Attachment SDRAM Synchronous Dynamic Random Access...

Page 23: ...ntel Celeron M Processor at 600 MHz Addendum to the Intel Celeron M Processor Datasheet http www intel com design intarch datashts 301753 htm ULV Intel Celeron M Processor at 600 MHz for Embedded Appl...

Page 24: ...24 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Introduction...

Page 25: ...rue plug and play for the platform Traditionally the ISA interface was used for audio and modem devices The addition of AC 97 allows the OEM to use software configurable AC 97 audio and modem coder de...

Page 26: ...essor FWH 8Mbit Dual Integrated 16550 UARTs DDR 266 333 CRT TPV DVO Flat Panel Up to 4 66 MHz PCI X Masters Up to 4 33 MHz PCI Masters Intel 6300ESB I O Controller 689 mBGA Intel 6300ESB I O Controlle...

Page 27: ...uency mode VCCA 1 8 V VCCP 1 05 V VCC CORE for Low Voltage Intel Pentium M Processor at 1 1 GHz 1 180 V highest frequency mode to 0 956 V lowest frequency mode VCCA 1 8 V VCCP 1 05 V TDP 24 5 W for th...

Page 28: ...Enhanced Intel SpeedStep Technology Deeper Sleep operation or Intel Thermal Monitor 2 2 3 4 Intel Celeron M Processor on 90 nm process Most features of the Intel Pentium M processor on 90 nm process...

Page 29: ...bit AGTL bus addressing no support for 36 bit address extension Supports Uni processor UP systems 400 MT s Pentium M processor FSB support 100 MHz 2X Address 4X Data 12 deep in order queue 2 3 6 2 Int...

Page 30: ...nel SSC support of 0 5 1 0 and 2 5 center and down spread with external SSC clock Supports data format of 18 bpp LCD panel power sequencing compliant with SPWG timing specification Compliant with ANSI...

Page 31: ...er Hub system consists of The I O Controller Hub Intel 6300ESB I O Controller Hub which provides the I O subsystem with access to the rest of the system Additionally it integrates many I O functions T...

Page 32: ...l 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Overview Hardware based locking Five GPIs 2 3 8 1 Packaging Power 32 pin TSOP PLCC 3 3 V core and 3 3 V 12 V for fast progr...

Page 33: ...hese wider spaces reduce settling time Coupling between two traces is a function of the coupled length the distance separating the traces the signal edge rate and the degree of mutual capacitance and...

Page 34: ...d where the speed critical interfaces such as the Intel Pentium M Celeron M Processor FSB or DDR system memory are routed In the remaining sections of the motherboard layout the Layer 4 and Layer 5 la...

Page 35: ...ning between layers next to the component the signal pins shall be accounted for by the GND stitching vias that would stitch all the GND plane layers in that area of the motherboard Due to the arrange...

Page 36: ...36 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide General Design Considerations...

Page 37: ...n M Processor FSB in your platform is by performing a comprehensive simulation analysis It is possible that adjustments to trace impedance line length termination impedance board stack up and other pa...

Page 38: ...sing a 2 1 ratio shown in Figure 4 would be acceptable only if additional simulations conclude that it is possible which may include some changes to the stack up or routing assumptions 4 1 1 3 Recomme...

Page 39: ...upling maximum value of 8 15 percent When the coupling results are greater than the maximum value additional system level simulations must be performed to avoid any signal quality issues due to crosst...

Page 40: ...For details on minimum motherboard trace length requirements refer to Section 4 1 2 1 and Table 3 for more details Intel recommends routing these signals on the same internal layer for the entire len...

Page 41: ...the longest common clock signal total trace lengths from the die pad of the processor to the associated die pad of the chipset For example ADS 997 mils board trace 454 Intel Pentium M Celeron M Proces...

Page 42: ...ynchronous signals requires careful attention to their routing considerations The following guidelines shall be strictly adhered to to ensure robust high frequency operation of these signals Figure 7...

Page 43: ...signals are routed on Layer 3 and Layer 6 Layer 2 and Layer 7 are solid grounds across the entire motherboard However this is not sufficient because significant coupling exists between signal layer La...

Page 44: ...6300ESB ICH Embedded Platform Design Guide Intel Pentium M Celeron M Processor FSB Design and Power Delivery Guidelines Figure 9 Layer 6 Intel Pentium M Celeron M Processor FSB Source Synchronous Data...

Page 45: ...In the socket cavity of the Intel Pentium M Celeron M Processor Layer 3 is used for VCC core power delivery to reduce the I R drop However outside of the socket cavity Layer 3 signals are routed belo...

Page 46: ...nes Figure 11 Layer 3 Intel Pentium M Celeron M Processor FSB Source Synchronous Signals GND Referencing to Layer 2 and Layer 4 Ground Planes Figure 12 Layer 3 Intel Pentium M Celeron M Processor FSB...

Page 47: ...ng underneath the GMCH and the Intel Pentium M Celeron M Processor package outlines and up to 200 300 mils outside the package outline The benefits of additional spacing include increased signal quali...

Page 48: ...ength of the address signals of their associated group In addition each address signal shall be trace length matched within 200 mils of its associated strobe signal Table 5 Intel Pentium M Celeron M P...

Page 49: ...red for GMCH Refer to Section 4 1 4 for length matching constraints and to Section 4 1 4 1 package length compensation for further details The Pentium M Celeron M processor package traces are routed a...

Page 50: ...l Group CPU Signal Name Intel Pentium M Celeron M Processor Package Trace Length mils GMCH Signal Name GMCH Package Trace Length mils Data Group 1 D15 721 HD15 554 D14 721 HD14 393 D13 721 HD13 494 D1...

Page 51: ...64 HD25 837 D24 564 HD24 493 D23 564 HD23 766 D22 564 HD22 731 D21 564 HD21 522 D20 564 HD20 714 D19 564 HD19 412 D18 564 HD18 834 D17 564 HD17 634 D16 564 HD16 593 DINV 1 564 DINV 1 628 DSTBP 1 564 H...

Page 52: ...608 D40 661 HD40 358 D39 661 HD39 655 D38 661 HD38 619 D37 661 HD37 747 D36 661 HD36 633 D35 661 HD35 675 D34 661 HD34 683 D33 661 HD33 501 D32 661 HD32 664 DINV 2 661 DINV 2 784 DSTBP 2 661 HDSTBP 2...

Page 53: ...8 HD57 649 D56 758 HD56 372 D55 758 HD55 541 D54 758 HD54 598 D53 758 HD53 469 D52 758 HD52 575 D51 758 HD51 326 D50 758 HD50 549 D49 758 HD49 511 D48 758 HD48 372 DINV 3 758 DINV 3 431 DSTBP 3 758 HD...

Page 54: ...A15 616 HA15 375 A14 616 HA14 562 A13 616 HA13 501 A12 616 HA12 522 A11 616 HA11 566 A10 616 HA10 560 A9 616 HA9 327 A8 616 HA8 333 A7 616 HA7 274 A6 616 HA6 523 A5 616 HA5 551 A4 616 HA4 352 A3 616 H...

Page 55: ...e tables as required to ensure adequate timing margins The amount of minimum to maximum length variance allowed for each group around the clock strobe reference length varies from signal group to sign...

Page 56: ...us section Length matching refers to constraints on the minimum and maximum length bounds of a signal group based on clock length whereas package length compensation refers to the process of adjusting...

Page 57: ...f the serpentine as shown in Figure 15 This operation generates a floating section of the serpentine 7 Use the Allegro Move ix i e if vertical routing command to move the floating section by the 2 dis...

Page 58: ...Datasheet or the Intel Celeron M Processor Datasheet Table 10 Asynchronous AGTL Nets Signal Names Description Topology CPU I O Type Output Output Buffer Type Input Input Power Well IERR Internal error...

Page 59: ...d layout recommendations Table 12 lists the recommended routing requirements for the FERR and THERMTRIP signals of the Intel Pentium M Celeron M processor The routing guidelines allow the signals to b...

Page 60: ...e translation between the Intel Pentium M Celeron M processor s PROCHOT signal and a system receiver that utilizes a 3 3 V interface voltage shown as V_IO_RCVR Series resistor Rs is a component of the...

Page 61: ...stration for Topology 2A Note The output from the AND Gate AND of power supply PWRGD_3V and CPU VR__PWRGD shall be routed point to point to the Intel Pentium M Celeron M processor s PWRGOOD signal The...

Page 62: ...implementation for providing voltage translation between the 6300ESB s INIT voltage signaling level and any firmware hub FWH that utilizes a 3 3 V interface voltage shown as a supply V_IO_FWH Refer t...

Page 63: ...re good signal quality and acceptable performance from the circuit In addition to providing voltage translation between driver and receiver devices the recommended circuit also provides filtering for...

Page 64: ...trated in Figure 24 shall be implemented The CPURESET signal from the GMCH shall fork out do not route one trace from GMCH pin and then T split towards the processor s RESET pin as well as toward the...

Page 65: ...mize the routing between Rs and Rtt as well as the minimal routing between Rs and the ITP700FLEX connector Also because a transition between Layer 6 and the secondary side occurs a GND stitching via i...

Page 66: ...CH s BCLK 1 0 signals a similar transition from Layer 3 to the secondary side layer is done next to the Intel 855GME chipset package outline Routing of the GMCH s BCLK 1 0 signals on the secondary sid...

Page 67: ...a reference voltage MCH_GTLREF to be supplied to its HVREF 4 0 pins The GTLREF voltage divider for both the Intel Pentium M Celeron M processor and GMCH cannot be shared Thus both the processor and G...

Page 68: ...ce voltage to the package These three pins have been renamed into RSVD pins and are required to be left as no connects on the platform RSVD signal pins E26 G1 and AC1 are to be left unconnected on Int...

Page 69: ...1 Pentium M Celeron M Processor AGTL I O Buffer Compensation For the Intel Pentium M Celeron M processor the COMP 2 and COMP 0 pins see Figure 29 each must be pulled down to ground with 27 4 1 resist...

Page 70: ...stor connects with an 18 mil wide Zo 27 4 and 260 mil long trace to COMP2 Necking down to 14 mils is allowed for a short length to pass in between the dog bones Notice that the COMP2 Figure 31 left si...

Page 71: ...PRIMARY SIDE SECONDARY SIDE VCCP to Odem VCCP VCCP One GND Via COMP 0 COMP 1 COMP 2 COMP 3 AA1 Y2 GND pins GTLREF 3 VCCA 1 8 v PRIMARY SIDE SECONDARY SIDE VCCP to Odem VCCP to 855GME VCCP VCCP VCCP V...

Page 72: ...rocessor s ITP signals TDI TMS TRST and TCK shall assume default logic values even if the ITP debug port is not used The TDO signal may be left open or no connect in this case Table 18 summarizes the...

Page 73: ...de of the motherboard To avoid GND via interaction with the Intel Pentium M Celeron M processor FSB routing the resistors share GND via connections with the A8 A17 and A20 ground pins of the Intel Pen...

Page 74: ...he recommended layout example 4 1 12 PLL Voltage Design for Low Voltage Intel Pentium M Processors on 90 nm process with 2 MB L2 Cache One primary difference between the Intel Pentium M processor 130n...

Page 75: ...t and debug groups in debugging various issues For this reason it is critical that ITP support is provided This may be done with zero additional BOM cost and minimal layout footprint costs The cost fo...

Page 76: ...s the locking mechanism may become inaccessible It is important to check the logic analyzer design guidelines to ensure a particular socket will work The logic analyzer was designed to accommodate the...

Page 77: ...M processor does differ from the default ITP debug port recommendations The changes described below should be adhered to closely 4 3 1 Recommended Onboard ITP700FLEX Implementation 4 3 1 1 ITP Signal...

Page 78: ...pull down to ground should be placed within 200 ps of the ITP700FLEX connector pin 5 Route the TDO signal from the Intel Pentium M Celeron M processor to a 54 9 1 percent pull up resistor to VCCP tha...

Page 79: ...d for the BPM 5 PREQ signal The maximum length of BPM 5 PREQ should not exceed 6 0 inches As explained in Section 4 1 6 the RESET signal forks see Figure 14 out from the 82855GME s CPURESET pin and is...

Page 80: ...age The ITP700FLEX VTT and VTAP pins should be shorted together and connected to the VCCP 1 05 V plane with a 0 1 F decoupling capacitor placed within 0 1 inch of the VTT pins Table 19 summarizes term...

Page 81: ...eron M processor s TCK pin and loops back with no stub to the FBO pin of the ITP700FLEX connector BCLKp BCLKn are routed in this example on Layer 3 For more BCLKp BCLKn routing details refer to Figure...

Page 82: ...ut pins followed by a pair of 49 9 1 percent termination resistors to ground Serpentining of the ITP_CLK traces is performed to meet the 50 ps length matching requirement between ITP_CLK and the sum o...

Page 83: ...t series resistor The series 33 and 49 9 1 percent parallel termination resistors on the ITP_CLK ITP_CLK differential host clock inputs to the ITP700FLEX connector may also be depopulated for producti...

Page 84: ...t shall be routed with a 150 to 240 pull up resistor placed within 1 ns of the ITP connector 4 3 2 1 ITP_CLK Routing to ITP Interposer A layout example for ITP_CLK ITP_CLK routing to the CPU socket fo...

Page 85: ...signer to determine whether termination for DBR is required or not for a given system implementation The same is also true for DBA if implemented This signal is not required and may be left as no conn...

Page 86: ...s as well as internal core timings i e maximum frequency Traditionally this supply is low pass filtered to prevent any performance degradation The Intel Pentium M Celeron M processor has an internal P...

Page 87: ...coupling capacitors to the VCCA1 pin A small ground plane connects the groundside of the 1206 form factor 10 F VCCA1 capacitors with a pair of vias to an internal ground plane The 10 F decoupling capa...

Page 88: ...ts Table 20 presents the VCCA 3 0 decoupling guidelines Figure 41 Intel Pentium M Celeron M Processor 1 8 V Intel Customer Reference Board Routing Example Table 20 VCCA 3 0 Decoupling Guidelines Descr...

Page 89: ...cessor power delivery circuit is a concern for system thermal and electrical design engineers The high input voltage low duty factor inherent in power supply designs leads to increasing power dissipat...

Page 90: ...pins 4 4 1 Transient Response The inductance of the motherboard power planes slows the voltage regulator s ability to respond quickly to a current transient Decoupling a power plane may be partitioned...

Page 91: ...ltage regulator decoupling capacitors and processor VCC CORE pins To meet the VCC CORE transient tolerance specifications for the worst case stimulus the maximum Equivalent Series Resistance ESR of th...

Page 92: ...et and Intel 6300ESB ICH Embedded Platform Design Guide Figure 42 Intel Pentium M Celeron M Processor Socket Core Power Delivery Corridor 49 VCC GND Pairs 24 VCC GND Pairs VR Feed 49 VCC GND Pairs 24...

Page 93: ...les shown in Table 21 and Figure 44 a low inductance value of 41 pH is achieved Bulk decoupling capacitors respond too slowly to handle the fast current transients of the processor For this reason 080...

Page 94: ...4 is a polymer covered aluminum and ceramic decoupling capacitor based solution that implements four polymer covered aluminum SP type capacitors that have a low ESR of 12 m each It also uses 35 x 10 F...

Page 95: ...e terminals of the SP capacitors Thirty two 10 F 0805 capacitors are placed on the secondary side Layer 8 while the remaining three are placed on the primary side Layer 1 Six of the 10 F capacitors ar...

Page 96: ...flood is as wide as the whole AF signal row and shall connect to all the VCC CORE pins in signal rows Y W V and U as illustrated in Figure 45 The remaining nine out of 32 10 F 0805 see Figure 44 capac...

Page 97: ...one is on the side closest to signal column 2 The area between these three capacitors may be efficiently used for VRM sense resistor connections as illustrated in the primary side zoom view in Figure...

Page 98: ...cavity shadow on the secondary side for both the north and south sides of the pin map as well as outside the socket shadow along the north power corridor pins Intel recommends the adoption of option 4...

Page 99: ...Side 90mil 90mil Sense Resistors VR feed 4x220uF SP Cap 100 mil 90 mil Primary Side SecondarySide 90 mil 90 mil Sense Resistors VR feed 4x220uF SP Cap L1 PS L2 GND L3 Sig L4 GND L5 PWR L6 Sig L7 GND L...

Page 100: ...package Ten 0 1 F X7R capacitors in a 0603 form factor shall be placed on the secondary side of the motherboard under the Intel Pentium M Celeron M processor socket cavity next to the VCCP pins of th...

Page 101: ...re power rail Power rail that is only on during full power operation These power rails are on when the PSON signal is asserted to the ATX power supply The core power rails that are distributed directl...

Page 102: ...102 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide...

Page 103: ...ilable during STR a thorough power budget shall be completed Power requirements shall include each device s power requirements both in suspend and in full power The power requirements shall be compare...

Page 104: ...mA Intel 6300ESB Vcc3 3 3 V 528 mA Vccsus3_3 3 3 V 142 mA S0 S1 S3 S5 IMVP IV 2 5V Regulator 3 3 V Standby Regulator 1 25 V Regulator 2 5 V Standby Regulator 1 5 V Standby Regulator 1 5 V Regulator V...

Page 105: ...wer Sequencing Requirements 4 7 2 1 V5REF 3 3V Sequencing V5REF is the reference voltage for 5 V tolerance on inputs to the 6300ESB V5REF must be powered up before Vcc3_3 or after Vcc3_3 within 0 7 V...

Page 106: ...ike anomaly will be observed 4 7 3 PCI X Power Sequencing The 1 5 V voltage must be valid before the first CLK66 pulse is driven into the 6300ESB ICH This can be guaranteed by gating the CK409 clocks...

Page 107: ...itors shall be placed as close to the package as possible Rotate caps that sit over power planes so that the loop inductance is minimized see Figure 51 The basic theory for minimizing loop inductance...

Page 108: ...The system memory interface also requires low frequency decoupling Place two 150 F electrolytic capacitors between the GMCH and the first DIMM connector Table 24 GMCH Decoupling Recommendations Pin N...

Page 109: ...an 100 mils from the termination resistors A VTT copper flood must be used The decoupling capacitors must be spread out across the termination rail so that all the parallel termination resistors are n...

Page 110: ...The DIMM connector 2 5 V pins as well as the GMCH 2 5 V power vias must connect to the 2 5 V copper flood In the areas where the copper flooding necks down around the GMCH make sure to keep these nec...

Page 111: ...MP Resistive Compensation The GMCH requires a system memory compensation resistor SMRCOMP to adjust buffer characteristics to specific board and operation environment characteristics Refer to the Inte...

Page 112: ...5 percent tolerant resistors are acceptable for this application Only signals from the same DDR signal group may share a resistor pack Refer to Section 5 for system memory guidelines 4 8 2 5 DDR SMRC...

Page 113: ...eference voltage HCCVREF Maximum length from pin to voltage divider for each reference voltage shall be less than 0 5 inches Ten mil wide traces are recommended GMCH VREF may be maintained as individu...

Page 114: ...ide Sample layout for GMCH VREF generation is shown in Figure 58 and Figure 59 Figure 57 GMCH HCCVREF Reference Voltage Generation Circuit R1 49 9 1 R2 100 1 C1 1uF VCCP Y28 Intel 855GME Chipset HCCVR...

Page 115: ...ignal 4 8 3 3 GMCH AGTL Reference Voltage The GMCH s AGTL I O buffer resistive compensation mechanism also requires the generation of reference voltages to the HXSWING and HYSWING pins with a value of...

Page 116: ...lies on the GMCH They are VCCASM VCCQSM VCCAHPLL VCCADPLLA VCCADPLLB VCCADAC VCCAGPLL and VCCALVDS VCCADAC VCCAGPLL and VCCALVDS do not require an RLC filter but do require decoupling capacitors Figur...

Page 117: ...s 100 F 0603 0 1 F X5R VCCQSM 1 In series with Cbulk 0805 0 68 H DCRmax 0 80 s 1206 4 7 F X5R 0603 0 1 F X5R VCCAHPLL None N A None 0603 0 1 F X5R VCCADPLLA 1 In series with inductor 0805 0 10 H 220...

Page 118: ...US1_5 1 5 V VCCSUS3_3 3 3 V V5REF_SUS 5 V V5REF 5 V USB VCC 5VSB 5 V 5 V PCI X PCI CNR VCC3 3 3 V VCC 5 V 12V 12 V 12V 12 V AC 97 5VSB 5 V 12V 12 V 12V 12 V Serial Ports VCC3 3 3 V 5V analog 5 V FWH S...

Page 119: ...mponents For 6300ESB preliminary power requirements on this rail see Table 26 For decoupling considerations see Section 4 8 9 Intel 6300ESB Decoupling Recommendations on page 120 Note This regulator i...

Page 120: ...e where a trace would serve as antennae 4 8 8 Intel 6300ESB Power Consumption Refer to the Intel 6300ESB I O Controller Hub Datasheet for power consumption information 4 8 9 Intel 6300ESB Decoupling R...

Page 121: ...VCC supply pins Note that the value of the low frequency bulk decoupling capacitor is dependent on board layout and system power supply design 4 9 Thermal Design Power Refer to the Intel 855GME Chipse...

Page 122: ...122 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide...

Page 123: ...b GMCH Datasheet for details on the signals listed Table 27 Intel 855GME Chipset DDR Signal Groups Group Signal Name Description Clocks SCK 5 0 DDR SDRAM differential clocks three per DIMM SCK 5 0 DDR...

Page 124: ...lines along with the exact length matching formulas and associated diagrams are provided in the individual signal group guidelines sections to follow An available DDR DIMM trace length calculator may...

Page 125: ...t based design The first group to be presented are the clocks because most of the signal groups have length formulas that are based on clock length 5 4 1 Clock Signals SCK 5 0 SCK 5 0 The clock signal...

Page 126: ...pin escapes only Minimum Pair to Pair Spacing See exceptions for breakout region below 20 mils Minimum Serpentine Spacing 20 mils Minimum Spacing to Other DDR Signals See exceptions for breakout regi...

Page 127: ...tal length for DIMM1 group X1 SCK to SCK Length Matching Match total length to 10 mils Clock to Clock Length Matching Total Length Match all DIMM0 clocks to X0 25 mils Match all DIMM1 clocks to X1 25...

Page 128: ...hs to which all clocks within the corresponding group are matched and the reference length values used to calculate the length ranges for the other signal groups 5 4 3 2 Clock Reference Lengths The cl...

Page 129: ...SCK3 Length X1 SCK 3 Length X1 SCK4 Length X1 SCK 4 Length X1 DIMM 0 DIMM 1 SCK3 SCK3 SCK4 SCK4 GMCH Package Note All lengths are measured from GMCH die pad to DIMM1 connector pads GMCH Package Lengt...

Page 130: ...e groups making for a total of eight 10 bit byte lanes This section summarizes the SDQ SDM to SDQS routing guidelines and length matching recommendations The data signals include SDQ 71 0 SDM 8 0 and...

Page 131: ...he DIMMs must be within the range defined in the overall guidelines and is also constrained by a length range boundary based on SCK SCK clock length and an SDQ SDM to SDQS length matching requirement...

Page 132: ...to Series Termination Resistor Pad Min 2 L2 Max 6 L3 L2 Trace Length L2 Series Termination Resistor Pad to First DIMM Pad Max 0 75 Total Length P1 L1 L2 Total Length from GMCH to First DIMM Pad Min 2...

Page 133: ...h including package length Refer to Section 5 4 1 for more information Y0 SDQS 7 0 total length GMCH package L1 L2 as shown in Figure 66 where X0 1 5 Y0 X0 0 5 Length range formula for DIMM1 X1 SCK 5...

Page 134: ...M0 connector L1 L2 plus package length For DIMM1 the motherboard trace length to the pads of the DIMM1connector L1 L2 L3 plus package length Length range formula for SDQ and SDM X SDQS total length in...

Page 135: ...ignals within a byte lane Byte lane mapping is defined in Table 33 5 4 4 4 SDQ to SDQS Mapping Table 33 defines the mapping between the nine byte lanes nine mask bits and the nine SDQS signals as requ...

Page 136: ...th Matching Diagram DIMM0 GMCH Package Note All lengths are measured from GMCH die pad to DIMM connector pad SDQ 0 SDQ 1 SDQ 2 SDQ 3 SDQS 0 SDQ 4 SDQ 5 SDQ 6 SDQ 7 SDQ Length Y X 25 mils SDQ Length Y...

Page 137: ...G20 730 SDQ 10 AG7 685 SDQ 42 AF22 562 SDQ 11 AE8 558 SDQ 43 AH22 702 SDQ 12 AF5 734 SDQ 44 AF20 563 SDQ 13 AH4 825 SDQ 45 AH19 644 SDQ 14 AF7 644 SDQ 46 AH21 716 SDQ 15 AH6 912 SDQ 47 AG22 783 SDQ 16...

Page 138: ...external layer to connect to the appropriate pad of the DIMM connector and the parallel termination resistor When the layout requires additional routing before the termination resistor return to the s...

Page 139: ...packs are acceptable for the parallel Rt control termination resistors but control signals cannot be placed within the same R pack as the data or command signals The table and diagrams below depict t...

Page 140: ...Signal Group SCKE 3 0 SCS 3 0 Motherboard Topology Point to Point with Parallel Termination Reference Plane Ground Referenced Characteristic Trace Impedance Zo 55 15 Nominal Trace Width Inner layers 4...

Page 141: ...ination resistor Figure 70 depicts the length matching requirements between the control signals and clock A nominal CS CKE package length of 500 mils may be used to estimate baseline Mbyte lengths Fig...

Page 142: ...external layer to an internal signal layer under the GMCH Keep the same internal layer until transitioning to an external layer immediately prior to connecting the DIMM0 connector pad At the via trans...

Page 143: ...Plane Ground Referenced Characteristic Trace Impedance Zo 55 15 Nominal Trace Width Inner layers 4 mils Outer layers 5 mils Minimum Spacing to Trace Width Ratio 2 1 e g 8 mil space to 4 mil trace Min...

Page 144: ...al total length GMCH package L1 L2 L3 as shown in Figure 71 where X1 1 5 Y1 X1 1 0 No length matching is required from DIMM1 to the termination resistor Figure 72 depicts the length matching requireme...

Page 145: ...Package SMA 12 6 3 0 SBA 1 0 SRAS SCAS SWE SCK 2 0 SCK 2 0 Note All lengths are measured from GMCH die pad to DIMM connector pad Clock Reference Length X0 DIMM0 DIMM1 SCK 5 3 SCK 5 3 Clock Ref Length...

Page 146: ...5 0 The GMCH drives the CPC and clock signals together with the clocks crossing in the valid control window The GMCH provides one set of CPC signals per DIMM slot Refer to Table 40 for the SMA and SMA...

Page 147: ...ard to simplify routing and minimize trace lengths All internal and external signals shall be ground reference to keep the path of return current continuous Intel suggests that all control signals be...

Page 148: ...ter Routing Guidelines Signal Group SMA 5 4 2 1 SMAB 5 4 2 1 Motherboard Topology Point to Point with Parallel Termination Reference Plane Ground Referenced Characteristic Trace Impedance Zo 55 15 Nom...

Page 149: ...ination resistor Figure 74 depicts the length matching requirements between the CPC signals and clock A nominal CPC package length of 500 mils may be used to estimate baseline Mbyte lengths Figure 74...

Page 150: ...all in order to facilitate probing 5 5 ECC Guidelines The GMCH may be configured to operate in an ECC data integrity mode that allows multiple bit error detection and single bit error correction This...

Page 151: ...s important that all relevant SDQ and SDQS signals to the DIMMs be disabled when the system is populated with only non ECC or a combination of ECC and non ECC memory In such cases the registers mentio...

Page 152: ...152 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide System Memory Design Guidelines DDR SDRAM...

Page 153: ...d for external buffering There is also an LC pi filter on each channel that is used to reduce high frequency noise and to reduce EMI In order to maximize the performance the filter impedance cable imp...

Page 154: ...1 percent terminating pull down resistor The complement signals R G and B shall be grounded to the ground plane Intel recommends that the pi filter and terminating resistors be placed as close as pos...

Page 155: ...d DAC Channel RED Motherboard GREEN Green DAC Channel GREEN BLUE Blue DAC Channel BLUE VGA Connector Pin 1 Pin 2 Green Pin 3 Blue Place components in Close proximity to VGA Place ESD diodes to minimiz...

Page 156: ...rd Components Component Value Tolerance Power Type R1 75 0 1 1 16 W SMT Metal Film Rset 128 0 1 1 16 W SMT Metal Film C1 0 1 F 20 SMT Ceramic C2 0 01 F 20 SMT Ceramic C 3 3 pF 10 SMT Ceramic D PAC DN0...

Page 157: ...to the VCCA_DAC Additional filtering and or separate voltage rail may be needed to do so Video DAC Power Supply DC Specification 1 50 V 5 percent Video DAC Power Supply AC Specification 0 3 percent fr...

Page 158: ...r converts up to 18 bits of parallel digital RGB data 6 bits per RGB along with up to 4 bits for control SHFCLK HSYNC VSYNC DE into two 4 channel serial bit streams for output by the LVDS transmitter...

Page 159: ...LVDS connector pin The reason for this is to compensate for the package length variation across each signal group in order to minimize timing variance The GMCH does not equalize package lengths inter...

Page 160: ...gth of 10 0 inches This maximum applies to all of the LVDS transmitter signals Traces must be ground referenced and must not switch layers between the GMCH and connector Table 46 LVDS Signal Group Rou...

Page 161: ...e variety of third party DVO compliant devices e g TV encoder TMDS transmitter or integrated TV encoder and TMDS transmitter The 82855GME has two dedicated Digital Video Out Ports DVOB and DVOC Intel...

Page 162: ...0 signals act as straps for an ADDID These pins are used to communicate to the Video BIOS when an external device is interfaced to the DVO port If an on board DVO device is implemented ADDID 7 should...

Page 163: ...The amount of minimum to maximum length variance allowed for each group around the clock strobe reference length varies from signal group to signal group depending on the amount of timing variation w...

Page 164: ...nds of a signal group based on clock length whereas package length compensation refers to the process of adjusting out package length variance across a signal group There is of course some overlap in...

Page 165: ...of 7 mils The signals shall be separated to a trace width of 4 mils and a trace spacing of 8 mils within 0 3 inches of the GMCH component Table 51 DVOB and DVOC Routing Guideline Summary Parameter De...

Page 166: ...BD 9 N3 504 DVOBD 10 M1 611 DVOBD 11 M5 510 DVOBFLDSTL M2 566 DVOBHSYNC T6 339 Table 53 DVOC Interface Package Lengths Signal Pin Number Package Length mils DVOCBLANK L3 541 DVOCCLK J3 601 DVOCCLK J2...

Page 167: ...data and the strobe respectively The DVO physical interface is a point to point topology using 1 5 V signaling The DVO uses a 165 MHz clock The flight time skew simulations reproduce all parameters th...

Page 168: ...ns 6 4 DVOB and DVOC Port Flexible Modular Design The GMCH supports flexible design interfaces described in this section 6 4 1 DVOB and DVOC Module Design The 82855GME supports a DVO module design con...

Page 169: ...ing guideline is the same as in Table 55 each strobe pair must be separated from other signals by at least 12 mils For multiplexed design more conservative length mismatch 0 1 inches is adopted 6 4 1...

Page 170: ...s are required except for LCLKCTRLA LCLKCTRLB GMBUS pair This prevents the GMCH DVOB interface from confusing noise on these lines for false cycles Table 56 GMBUS Pair Mapping and Options Pair Signal...

Page 171: ...and Voltage Reference ADDID 7 Pull down to ground with a 1 K resistor when using the DVOB or DVOC port This is a vBIOS strapping option to load the TPV AIM module for DVOB and DVOC port Pull down not...

Page 172: ...172 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Integrated Graphics Display Port...

Page 173: ...s It is possible to use the DVO ports in dual channel mode to support higher resolutions and refresh rates single channel mode is limited to a 165 MHz pixel clock rate 7 1 1 AGP 2 0 The AGP Interface...

Page 174: ...timing domain signals 2X 4X timing domain signals and miscellaneous signals will be addressed separately Table 57 AGP 2 0 Signal Groups 1x Signals 2x Signals 4x Signals CLK 3 3 V GRBF GWBF GST_ 2 0 GP...

Page 175: ...in signals see Table 59 can be routed with 4 mil minimum trace separation 7 2 1 3 Trace Length Mismatch There are no trace length mismatch requirements for 1X timing domain signals These signals must...

Page 176: ...e signals AD_STB0 AD_STB0 AD_STB1 AD_STB1 SB_STB and SB_STB act as clocks on the source synchronous AGP interface special care should be taken when routing these signals Because each strobe pair is tr...

Page 177: ...compliment must be the same length within 0 01 inches Table 62 shows the AGP 2 0 routing summary 7 2 3 AGP Clock Skew The maximum total AGP clock skew between the GMCH and the graphics component is 1...

Page 178: ...ace spacing may be reduced as the traces go around each capacitor The narrowing of space between traces should be minimal and for as short a distance as possible 1 0 inch max In addition to the minimu...

Page 179: ..._STB1 AD_STB1 SB_STB SB_STB G_TRDY G_IRDY G_GNT ST 2 0 GAD18 L3 541 GCBEB_3 J5 518 GAD19 K5 489 GST_0 C4 750 GAD20 K1 692 GST_1 C3 797 GAD21 K3 622 GST_2 C2 856 GAD22 K2 685 GRBFB D3 962 GAD23 J6 536...

Page 180: ...es not implement the PERR and SERR signals Pull ups on the motherboard are required for AGP graphics controllers that implement these signals 3 The Intel chipset GMCH does not implement interrupt sign...

Page 181: ...o reduce crosstalk and maintain signal integrity 7 2 10 AGP Compensation The 855GME chipset GMCH AGP interface supports resistive buffer compensation For PCBs with characteristic impedance of 55 tie t...

Page 182: ...t and Intel 82801DB ICH4 Embedded Platform Design Guide AGP Port Design Guidelines Figure 84 DPMS Circuit AGP_TYPEDET 8 AGP_PIPE _FET V12S 17 23 27 37 45 Q6D1 BSS138 3 1 2 Q6D2 BSS138 3 1 2 PM_SUS_CLK...

Page 183: ...ting guidelines are created using the stack up described in Figure 2 Recommended Board Stack up Dimensions on page 34 8 1 8 Bit Hub Interface Routing Guidelines 8 1 1 8 Bit Hub Interface Data Signals...

Page 184: ...ur options are given for the divider circuit choose the one that best supports your platform Table 67 Hub Interface 1 5 Strobe Signals Routing Summary Strobe Signal Requirements Maximum Trace Length R...

Page 185: ...ivider to device is four inches less is better Normal care needs to be taken to minimize crosstalk to other signals 10 15 mV When the single HIREF HI_VSWING divider circuit is located more than four i...

Page 186: ...ING pin C2 1 Two 0 1 F capacitors C1 and C3 should be placed close to the divider 2 Each 0 01 F bypass capacitor C2 C4 C5 and C6 should be placed within 0 25 inches of HIREF VREF pin for C4 and C6 and...

Page 187: ...ust meet the voltage specification in Table 68 The resistor values R1 R2 and R3 must be rated at 1 percent tolerance see Table 69 Normal care needs to be taken to minimize crosstalk to other signals 1...

Page 188: ...ING divider circuits for GMCH Table 69 Recommended Resistor Values for Single VREF VSWING Divider Circuit Recommended Resistor Values VCCHI Option 1 R1 80 6 1 R2 51 1 1 R3 40 2 1 1 5 V Option 2 R1 255...

Page 189: ...ery use two 0 1 F capacitors per each component i e the 6300ESB and GMCH These capacitors should be placed within 50 mils from each package adjacent to the rows that contain the Hub Interface When the...

Page 190: ...190 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Hub Interface...

Page 191: ...t use and or duplicate clocks 8 No 90 degree bends or stubs 9 The allowable breakout region is 500 mils from the package 10 Do not route SATA traces through connectors or any other obstruction that wo...

Page 192: ...suffers significant signal attenuation and an increase in inter symbol interference 9 1 1 5 SATA BIAS Connections It is recommended that the SATARBIASP and the SATARBIASN pins be shorted at the packag...

Page 193: ...external pull up to Vcc3 3 When low SATALED indicates SATA device activity and should activate the hard drive LED When tri stated the signal will not activate the LED Note Ensure that all connectors a...

Page 194: ...h 5 mil width traces 7 mil spacing dependent upon stackup parameters and must be less than eight inches long from 6300ESB to IDE connector See Table 75 below for routing summary Note A max of two laye...

Page 195: ...obtained from the Small Form Factor Committee To determine when Ultra DMA modes greater than two Ultra ATA 33 may be enabled the 6300ESB requires the system software to attempt to determine the cable...

Page 196: ...a legacy slave Device 1 is preventing proper cable detection and BIOS should configure the system as though a 40 conductor cable is present and notify the user of the problem 9 3 2 Device Side Cable D...

Page 197: ...istor The drive samples the signal after releasing it In an 80 conductor cable PDIAG CBLID is not connected through to the host and therefore the capacitor has no effect In a 40 conductor cable the si...

Page 198: ...7K pull up resistor to VCC3 3 is required on PIORDY Series resistors are not required but may be placed on the control and data line to improve signal quality Place the resistors as close to the conne...

Page 199: ...3 A 4 7 K pull up resistor to VCC3 3 is required on SIORDY Series resistors are not required but may be placed on the control and data line to improve signal quality Place the resistors as close to th...

Page 200: ...12 outgoing and 12 incoming data streams or slots The architecture of the 6300ESB AC link allows a maximum of three codecs to be connected Figure 99 shows a three codec topology of the AC link for th...

Page 201: ...ing from S1 S5 through the AC 97 link The codec asserts AC_SDIN to wake the system To provide wake capability and or caller ID standby power must be provided to the modem codec The 6300ESB has pull do...

Page 202: ...97 AC_SDOUT AC_SYNC Routing Summary Trace Impedance AC 97 Routing Requirements Trace Lengths Series Termination Resistance AC_SDOUT AC_ SYNC Signal Length Matching 55 10 5 mil width 10 mil spacing bas...

Page 203: ...alog power regulators over the analog ground plane The split between planes must be a minimum of 0 05 inches wide Keep digital signal traces especially the clock as far as possible from the analog inp...

Page 204: ...ave been developed to ensure maximum flexibility for board designers while reducing the risk of board related issues These recommendations are not the only implementation or a complete checklist but t...

Page 205: ...t reset Therefore its default state is a logical zero or set to reboot To disable the feature a jumper may be populated to pull the signal line high see Figure 103 The value of the pull up must be suc...

Page 206: ...TOP_SWAP bit bit 5 D31 F0 Offset D5h The SIU0_DTR signal has a weak integrated pull up resistor the resistor is only enabled during boot reset Therefore its default state is a logical zero or set to...

Page 207: ...ess of the state of the CDC_DN_ENAB signal On a motherboard containing an AC 97 Controller supporting three AC 97 Codecs the AC 97 Revision 2 2 codec on the motherboard must be connected to the SDATA_...

Page 208: ...208 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Intel 6300ESB Design Guidelines Figure 105 Motherboard AC 97 CNR Implementation with a Single Codec Down On Board...

Page 209: ...CDC_DN_ENAB Motherboard CNR 1 2 Compliant To GPIO AC_SDIN0 AC_SDIN1 AC_SDIN2 R 10K CNR Connector From Intel 6300ESB I O Cntrlr Hub To Intel 6300ESB I O Cntrlr Hub Table 81 CNR Routing Summary Trace I...

Page 210: ...k synthesizers magnetic devices or ICs that use and or duplicate clocks 6 Stubs on High speed USB signals should be avoided as stubs will cause signal reflections and affect signal quality When a stub...

Page 211: ...stackup being used keeping in mind the target differential impedance 3 Minimize the length of high speed clock and periodic signal traces that run parallel to High speed USB signal lines to minimize...

Page 212: ...Table 83 and Table 84 provide trace length guidelines 9 6 1 6 1 Platforms With A Nominal Impedance Of 55 10 Microstrip NOTE Two options are given for motherboard trace length choose the parameters th...

Page 213: ...gnals 25 mils of any anti etch to avoid coupling to the next split or radiating from the edge of the PCB When breaking signals out from packages it is sometimes very difficult to avoid crossing plane...

Page 214: ...6 2 2 GND Plane Splits Voids and Cut Outs Anti Etch Avoid anti etch on the GND plane 9 6 3 USB Power Line Layout Topology The following is a suggested topology for power distribution of VBUS to USB p...

Page 215: ...chosen and the frequency and strength of the noise present on the USB traces that you are trying to suppress 2 Once you have a part that gives passing EMI results the second step is to test the effec...

Page 216: ...h signal pairs that share a common jacket may combine VBUS and ground wires into a single wire provided the following conditions are met a The bypass capacitance required by Section 7 2 4 1 of the Uni...

Page 217: ...lems with the adjacent port sharing the same cable See sections 7 2 2 and 7 2 4 1 of the Universal Serial Bus Specification Revision 2 0 for more details Note Cables that contain more than two signal...

Page 218: ...be at least 50 mils wide to ensure adequate current carrying capability There should be double vias on power and ground nets and the trace lengths should be kept as short as possible 9 6 6 3 Front Pan...

Page 219: ...ection 9 6 1 Layout Guidelines on page 210 6 Trace length guidelines are given in Table 84 and Table 85 9 7 Low Pin Count LPC Interface The 6300ESB implements a Low Pin Count LPC Interface compliant w...

Page 220: ...r split in the ground plane may cause signal reflections and should be avoided 3 Route LPC signals using a minimum of vias and corners This reduces reflections and impedance changes 4 No 90 degree ben...

Page 221: ...he Intel 82562EM 82562EX Platform LAN Connect Component it will claim the SMLink heartbeat and event messages and send them out over the network An external Alert on LAN2 enabled LAN Controller e g In...

Page 222: ...capabilities when designing SMBus segments Routing SMBus to the PCI slots makes the design process even more challenging since they add so much capacitance to the bus This extra capacitance has a larg...

Page 223: ...by the core and suspend supplies See Figure 117 NOTES 1 Added considerations for mixed architecture 2 The bus switch must be powered by VCC_SUSPEND 3 Devices powered by the VCC_SUSPEND well must not...

Page 224: ...lines Note These routing guidelines are created using the stack up described in Section 3 1 Nominal Board Stack Up on page 33 Table 89 Bus Capacitance Reference Chart Device of Devices Trace Length Ca...

Page 225: ...with one of the PCI slots However it will not take away from the slot functionality unless the CNR slot is occupied by a CNR card Figure 118 PCI Bus Layout Example Figure 119 PCI Bus Layout Example wi...

Page 226: ...1 0 inch 4 Slots W1 W2 0 5 inches R_IDSEL 300 to 900 10 inches 1 0 inch 1 0 inch 1 0 inch Figure 120 PCI 33MHz Clock Layout Example Table 92 PCI 33 MHz Clock Signals Routing Summary Trace Impedance P...

Page 227: ...Controller Hub s internal devices functions but at a higher latency cost Table 93 IOAPIC Interrupt Inputs 16 through 23 Usage No IOAPIC INTIN PIN Function in 6300ESB using the PCI IRQ in IOAPIC 1 IOA...

Page 228: ...outed with 5 mils traces on 12 mils spaces dependent upon stackup parameters and must be less than eight inches long from 6300ESB to PCI X connector Trace spacing of 5 mils is only acceptable when nec...

Page 229: ...ure 122 66 MHz PCI X Two Slots Two Down Devices Configuration Table 97 66 MHz PCI X Two Slots Two Down Devices Routing Length Parameters Segment Length inches Total Routing Length L1 2 8 0 L2 1 5 Maxi...

Page 230: ...commended pull up value for the PXPCICAP signal is 4 7 K Table 98 66 MHz PCI X One Down Device Routing Length Parameters Segment Length inches L1 2 8 0 Figure 124 66 MHz PCI X Three Slot Configuration...

Page 231: ...ence and must be matched to the other clocks The length of the sum of TL1 TL2 must be matched to within 0 1 inch between all clocks passing to PCI X connectors For down devices and the PXPCLKI feedbac...

Page 232: ...lowing should be considered The SBR pin PCIXSBRST Ball AA7 may be left as a No Connect The PCI X slots should be tied to the system reset logic PXPCIRST 9 10 4 PME Signal Sharing In many cases the sys...

Page 233: ...ll as generate a free running full swing clock output for system use This output ball of the 6300ESB is called SUSCLK This is illustrated in Figure 127 For further information on the RTC consult Appli...

Page 234: ...es for C1 and C2 must be based on the crystal maker recommendations Typical values for C1 and C2 are 18 pF based on crystal load of 12 5 pF 2 Reference designators are arbitrarily assigned 3 3 3 V Sus...

Page 235: ...ese values depend on the characteristics of board material the width of signal traces and the length of the traces A typical value based on a 5 mil wide trace and a ounce copper pour is approximately...

Page 236: ...5 below room temperature is the same when operating at 50 C 25 C above room temperature 9 11 3 RTC Layout Considerations Since the RTC circuit is very sensitive and requires a highly accurate oscillat...

Page 237: ...nnected to the 6300ESB through an isolation Schottky diode circuit The Schottky diode circuit allows the 6300ESB RTC well to be powered by the battery when the system power is not available but by the...

Page 238: ...is combined with the diode circuit shown in Figure 130 to allow the RTC well to be powered by the battery when the system power is not available Figure 131 is an example of this circuitry that is used...

Page 239: ...weak external pull down to ground and INTRUDER should have a weak external pull up to VCCRTC This prevents these nodes from floating in G3 and correspondingly prevents ICCRTC leakage that may cause e...

Page 240: ...t is necessary to keep the 6300ESB in subtractive decode mode When a PCI boot card is inserted and the 6300ESB is programmed for positive decode there are two devices positively decoding the same cycl...

Page 241: ...12 V VPP for 80 hours 3 3 V on Vpp does not affect the life of the device The 12 V VPP would be useful in a programmer environment which is typically an event that occurs very infrequently much less...

Page 242: ...tion 9 14 GPIO Summary The 6300ESB platform has 12 general purpose inputs 9 general purpose outputs and 16 general purpose inputs outputs Figure 134 FWH VPP Isolation Circuitry B1191 01 FET 1 K from M...

Page 243: ...utput 3 3 V 28 Resume Input Output 3 3 V 32 Core Input Output 3 3 V 33 Core Input Output 3 3 V 34 Core Input Output 3 3 V 35 Core Input Output 3 3 V 36 Core Input Output 3 3 V 37 Core Input Output 3 3...

Page 244: ...be used to implement front panel reset 9 15 2 PWRBTN Usage Model The Power Button ball PWRBTN on the 6300ESB may be connected directly to the power button on the system front panel This signal is inte...

Page 245: ...ailure to implement this circuit or a circuit that functions similar to this may result in excessive droop on the VCCRTC node during Sx to G3 power state transitions removal of AC power Droop on this...

Page 246: ...246 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Intel 6300ESB Design Guidelines...

Page 247: ...ting much of the required glue logic into a single device overall board cost may be reduced Features include Dual strapping selectable feature sets Audio disable circuit Mute audio circuit 5 V referen...

Page 248: ...ME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Miscellaneous Logic 10 2 Discrete Logic As an alternative solution discrete circuitry may be implemented into a design instead of using...

Page 249: ...rms the CK409 is configured in the unbuffered mode and a host clock swing of 710 mV Table 104 Individual Clock Breakdown Clock Group Frequency Driver Pin Receiver s Comments HOST_CLK 100 MHz CK409 CPU...

Page 250: ...tion Diagram B1364 01 CPU ITP USBCLK CLK14 CLK66 CLK66 CLK33 Intel 855GME Chipset CK409 Intel 6300ESB I O Controller Intel 855GME Chipset Clock Distribution 100 MHz 66 MHz 48 MHz PLL SSCCLK 100 MHz Ou...

Page 251: ...ately steering a programmable constant current to the external termination resistors Rt The resulting amplitude is determined by multiplying IOUT by the value of Rt The current IOUT is programmable by...

Page 252: ...its L4 L4 2 0 to 8 0 Total Length Range L1 L2 L4 2 0 to 8 5 Length Matching Required Yes Pin to Pad HCLK to HCLK Length Matching 10 mils per segment 10 mils overall CPU Clock to GMCH Clock Length Matc...

Page 253: ...be matched as close as possible in total length from CK409 pin to the die pad of the receiving device In addition the L1 L1 segments of all three clock pairs should be length matched to within 10 mil...

Page 254: ...Inner Layer Trace Width 4 0 mils Nominal Outer Layer Trace Width 5 0 mils pin escapes only Minimum Spacing See exceptions below 20 mils Serpentine Spacing 20 mils Maximum Via Count 4 per side Series...

Page 255: ...ts Parameter Definition Class Name CLK33 Class Type Individual Nets Topology Series Terminated Point to Point Reference Plane Ground Referenced Single Ended Trace Impedance Zo 55 15 Nominal Inner Laye...

Page 256: ...Class Type Individual Nets Topology Series Terminated Point to Point Reference Plane Ground Referenced Single Ended Trace Impedance Zo 55 15 Nominal Inner Layer Trace Width 4 0 mils Nominal Outer Laye...

Page 257: ...s Type Individual Nets Topology Dual Series Terminated Point to Point Reference Plane Ground Referenced Single Ended Trace Impedance Zo 55 15 Nominal Inner Layer Trace Width 4 0 mils Nominal Outer Lay...

Page 258: ...Ended Trace Impedance Zo 55 15 Nominal Inner Layer Trace Width 4 0 mils Nominal Outer Layer Trace Width 5 0 mils pin escapes only Minimum Spacing See exceptions below 25 mils Maximum Via Count 4 Seri...

Page 259: ...ameter Definition Class Name SSCCLK Class Type Individual Net Topology Series Terminated Point to Point Reference Plane Ground Referenced Single Ended Trace Impedance Zo 55 15 Nominal Inner Layer Trac...

Page 260: ...nts Parameter Definition Class Name USBCLK Class Type Individual Net Topology Series Terminated Point to Point Reference Plane Ground Referenced Single Ended Trace Impedance Zo 55 15 Nominal Inner Lay...

Page 261: ...scheme Parallel Rt resistors perform a dual function converting the current output of the clock driver to a voltage and matching the driver output impedance to the transmission line The series resist...

Page 262: ...egrade the noise rejection of the network 3 Set line width to meet correct motherboard impedance The line width value provided here is a recommendation to meet the proper trace impedance based on the...

Page 263: ...ts on the same physical routing layer referenced to ground If a layer transition is required make sure skew induced by the vias used to transition between routing layers is compensated in the traces t...

Page 264: ...264 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Platform Clock Routing Guidelines...

Page 265: ...cessor Checklist 12 1 1 Connection Recommendations Table 115 presents the connection recommendations Figure 148 depicts the routing illustration for INIT for Intel Pentium M Celeron M processor Figure...

Page 266: ...Required Driver isolation resistor Rs shall be placed at the beginning of the T split to the system receiver Refer to Figure 149 PSI May be left as NC if not used for IMVP PWRGOOD 330 pull up to VCCP...

Page 267: ...el IMVP IV specification power supply VCCA 3 0 Connect to V1P8 The Low Voltage Intel Pentium M Processor on 90 nm process with 2 MB L2 cache will support a Vcca of 1 8V or 1 5V VCC1_05 25 1 Connect to...

Page 268: ...cycled when DBR is asserted RESET 220 5 pull up to VCCP when using ITP700FLEX 22 6 1 from pull up to ITP700FLEX Refer to the RESET notes in Table 115 FBO Connect to TCK pin of processor Refer to Sect...

Page 269: ...cap KO Cap 4 x 10 F Place one 10 F and one 0 01 F for each VCCA pin High Frequency Decoupling 0603 MLCC X7R Place next to Pentium M processor 4 x 0 01 F Place one 10 F and one 0 01 F for each VCCA pin...

Page 270: ...g 2 When deciding on overall decoupling solution customers may need to take layout and PCB board design into consideration 3 Option 4 is to be used with small footprint 100 mm2 or less 0 36 H 20 induc...

Page 271: ...PWRDWN Terminate to VCC3_CLK through 1 K resistor The Intel CRB does not support S1M state REF 0 1 33 5 This is the 14 318 MHz clock reference signal for the 6300ESB SIO and LPC Each receiver require...

Page 272: ...T Connect to DIMM 0 and DIMM 1 SRAS 56 pull up to V_1P25_MEMVTT Connect to DIMM 0 and DIMM 1 SWE 56 pull up to V_1P25_MEMVTT Connect to DIMM 0 and DIMM 1 SCKE 1 0 56 pull up to V_1P25_MEMVTT Connect t...

Page 273: ...er to Section 5 5 1 for information regarding GMCH clock routing flexibility SCK5 SCK5 Route these signals differentially directly to DIMM 1 Alternatively refer to Section 5 5 1 for information regard...

Page 274: ...5GME SMVREF signal Signal voltage level V_2P5_SM 2 Place a 0 1 F cap by GMCH DIMM 0 and DIMM 1 pins VDD 9 1 Connect to V_2P5_SM Power must be provided during S3 VDDSPD Connect to V_2P5_CORE SA 2 1 Con...

Page 275: ...0 F 100 F 9 15 4 3 1 A minimum of nine high frequency caps are recommended to be placed between the DIMMS A minimum of four low frequency caps are required Refer to section Section 4 8 3 2 for more in...

Page 276: ...o VCCP 150 1 pull down to GND Signal voltage level 1 3 of VCCP C1a 0 1 F C1b 0 1 F Refer to Figure 151 HYSWING 301 1 pull up to VCCP 150 1 pull down to GND Signal voltage level 1 3 of VCCP C1a 0 1 F C...

Page 277: ...ING HYSW ING 301 1 150 1 C1b VCCP HYSW ING Table 125 Hub Interface Checklist Pin Name System Pull up Pull down Notes Hl 10 0 Connect to the 6300ESB HI 10 0 signals Refer to Section 8 1 for more inform...

Page 278: ...ANELVDDEN 100 k pull down Used for LVDS Panel Power control PANELBKLTEN 100 k pull down Used for LVDS Panel backlight enable PANELBKLTCTL 100 k pull down Used for LVDS Panel backlight brightness contr...

Page 279: ...is unused 10K 100K For AGP this signal is GAD 14 MI2CCLK MI2CDATA 2 2 K pull up to V_1P5_CORE Pull up resistor required on each signal even if they are unused 2 2 K 100 K This signal is 1 5 V tolerant...

Page 280: ...ite bead 3 3 pF cap to GND Ferrite bead 75 at 100 MHz Ferrite bead for EMI suppression between GMCH and VGA connector BLUE On GMCH side of ferrite bead 75 1 pull down to GND 3 3 pF cap to GND ESD diod...

Page 281: ...2k pull up to Vcc5 after translation logic CRT DDC Clock Data Needs to be translated from 3 V to 5 V EXTTS_0 10 K 1 pull up to VCC3 LCLKCTLB Used for SSC chip data control on Intel CRB Leave this sig...

Page 282: ...m power supply to GMCH pins with caps on GMCH side of inductor VCC_DVO 16 1 Connect to V_1P5_CORE 0 1 F 10 F 150 F 2 1 1 Bulk decoupling is based on VR solutions used on CRB design VCC_ADAC 2 1 Connec...

Page 283: ...mpact PXAD 32 63 8 2 K pull up resistors to VCC3 3 May leave as no connect PXAD 0 31 No extra pull ups needed May leave as no connect PXPCICLK Ensure this pin is connected to a 66MHz clock output of t...

Page 284: ...esistor to VCC3 3 8 2 K pull up resistor to VCC3 3 PXIRDY 8 2 K pull up resistor to VCC3 3 8 2 K pull up resistor to VCC3 3 PXPAR No extra pull ups needed May leave as no connect PXPAR64 8 2 K pull up...

Page 285: ...ecification rev 1 0a PCIXSBRST When utilizing this pin ensure the circuit shown in Section 9 10 3 is implemented Connected to all devices that reside on the PCI X bus May leave as no connect The exter...

Page 286: ...n 8 2 K pull up resistor to VCC3 3 or a 2 7 K pull up resistor to VCC5 See PCI 2 2 Component Specification pull up recommendations for VCC3 3 and VCC5 PIRQ H E GPIO 5 2 Recommend a 2 7 K pull up resis...

Page 287: ...RQ D is connected to IRQ19 REQ 0 3 Recommend an 8 2 K pull up resistor to VCC3 3 or a 2 7 K pull up resistor to VCC5 Recommend an 8 2 K pull up resistor to VCC3 3 or a 2 7 K pull up resistor to VCC5 S...

Page 288: ...a 52 3 1 when trace impedance is 60 or 48 7 1 when trace impedance is 56 or 43 2 1 when impedance is 50 pull up resistor to VCC1_5 ZCOMP is no longer supported HIREF 350 mV See voltage divider recomme...

Page 289: ...s must be pulled up to VCCSus3 3 These signals are NOT 5 V tolerant GPO 16 23 These pins are in the Core Power Well Fixed as output only May be left NC GPO 16 17 may be used as GNT 2 3 These signals a...

Page 290: ...uld be connected to power monitoring logic and should go high no sooner than 100 ms after both VCC3 3 and VCC1_5 have reached their nominal voltages Timing Requirement RSMRST Recommend a 10 K pull dow...

Page 291: ...up to Vcc3 3 Table 139 CPU Signals Checklist Checklist Items Recommendations Reason Impact A20GATE Pull up signal to VCC3 3 through a 10 K resistor or If software control of A20M is desired connect to...

Page 292: ...d SMLINK 1 to SMBDATA Value of pull up resistors determined by line load To be fully compliant with the SMBus 2 0 specification which requires the Host Notify cycle the SMLink and SMBus signals must b...

Page 293: ...Function TOP Swap See the 6300ESB EDS for more information Pull down to GND to use TOP Swap function Value depends on platform specifics SIU1_DTR No extra pull ups needed May leave as no connect Inter...

Page 294: ...rong pull up will be required to override this internal pull down AC_SDIN 2 Requires a 10 K pull down to GND when a CNR card is used on the platform Series termination resistors 33 to 47 from the AC_S...

Page 295: ...nnect a 33 series resistor between the CK409 this signal May leave as no connect SATALED Recommend a weak external pull up to Vcc3 3 May leave as no connect Open Drain signal SATARBIASN Short this sig...

Page 296: ...sistors Pull up to VCC3 3 through 4 7 K resistors These signals have integrated series resistors in the 6300ESB IRQ14 IRQ15 Recommend 8 2 K to 10 K pull up resistors to VCC3 3 No extra series terminat...

Page 297: ...0 1 F decoupling cap V5REF is the reference voltage for 5 V tolerant inputs in the 6300ESB V5_REF must power up before or simultaneous to VCC3 3 It must power down after or simultaneous to VCC3 3 Pro...

Page 298: ...298 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Schematic Checklist Summary...

Page 299: ...ical supporting circuitry This is not a complete list and it does not ensure that a design will function properly Refer to details in this document and the appended Customer Reference Board schematics...

Page 300: ...Trace length match address strobes to 200 mils of average length of their associated address signals group AGTL Source Synchronous Signals Refer to Section 4 1 3 for more information ADS BNR BR0 DBSY...

Page 301: ...Intel 6300ESB Recommend connecting processor signal THERMTRIP to the 6300ESB but may be connected to any optional system receiver with consideration for any voltage level translation if necessary May...

Page 302: ...t Probe ITP Signals for ITP700FLEX Debug Port BPM 3 0 PRDY PREQ Route as a point to point transmission line connections from CPU pins to the ITP700FLEX connector via Zo 55 15 traces Limit trace length...

Page 303: ...mber of routing layer transitions should be minimized When layout constraints require a routing layer transition any such transition shall be accompanied with ground stitching vias placed within 100 m...

Page 304: ...hed to the GMCH BCLK BCLK signals When routing the 100 MHz differential clocks do not split up the two halves of a differential clock pair between layers and route to all agents on the same physical r...

Page 305: ...mmendations Processor Power and GND Measurement Sense Signals VCCSENSE VSSSENSE Route traces of equal length using 3 1 spacing Zo 55 15 Place via next to the processor socket s pin for measurement of...

Page 306: ...ced on the secondary side within the CPU package outline Refer to Section 4 4 4 for processor VCCP decoupling recommendations NOTES 1 A 31 3 pins on the processor correspond to HA 31 3 pins on the GMC...

Page 307: ...Refer to the detailed discussion on this topic in Section 5 4 3 Route as closely coupled differential pairs 3 clock pairs to each DIMM Spacing to other DDR signals should not be less than 20 mils Isol...

Page 308: ...edance 55 15 using 2 1 spacing Isolation from non DDR signals should be 20 mils GMCH pad to DIMM trace length limits are 2 to 6 inches Place parallel termination resistor within 2 inches of DIMM pad O...

Page 309: ...Requires a minimum of 11 0603 0 1 F caps placed within 150 mils of the GMCH package Distribute evenly along the DDR memory interface placed perpendicular to the GMCH with the power side of the caps f...

Page 310: ...g and VSS reference Route hub interface strobe and its complement as a differential pair length matched within 10 mils Maximum length for both data and strobe signals is 6 inches Hub interface data an...

Page 311: ...eration The case is similar for HIREF and HIVSWING signals on 6300ESB Refer to Section 8 1 4 for HI specific voltage requirements and several options for voltage divider circuits HXRCOMP HYRCOMP Each...

Page 312: ...0 pins on the processor 7 HADSTBP 3 0 pins on the GMCH correspond to DSTBP 3 0 pins on the processor 8 HREQ 4 0 pins on the GMCH correspond to REQ 4 0 pins on the processor 9 The HTRDY pin on the GMCH...

Page 313: ...er signals that might be coupling to them 6 Keep SATA signals clear of the core logic set High current transients are produced during internal state transitions These transients may be difficult to fi...

Page 314: ...t route USB traces under crystals oscillators clock synthesizers magnetic devices or ICs that use and or duplicate clocks 6 Stubs on USB signals should be avoided as stubs will cause signal reflection...

Page 315: ...backpanel should not exceed recommend length 17 Maximum length from the 6300ESB to the CNR should not exceed recommend length 18 Maximum length from the 6300ESB to the Front Panel connector should not...

Page 316: ...edge to edge Table 157 PCI Layout Checklist Layout Recommendations Comments 1 Ten inches maximum to the first slot then one inch to each subsequent slot PCI clocks and loop back clocks are scaled acc...

Page 317: ...list Table 159 Power Delivery Checklist Layout Recommendations Comments 1 Standby power rails V5REF_Sus VccSus3_3 should be implemented though planes Will reduce trace antennae effect 2 Decoupling cap...

Page 318: ...318 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist...

Page 319: ...of 2 CORE CPU Connector 2 of 2 CORE CPU Pull Ups PLL Circuitry TJPRO Connector CORE GMCH CORE GMCH Circuitry CORE GMCH PLL Straps LVDS Clock Generation CORE DDR Series Termination CORE DIMM Connector...

Page 320: ...S 2 SIO Parallel Port SIO COM1 FWH MFG Mode and Recovery Jumpers GLUE4 PC Speaker Front Panel Header Mounting Holes FAN Fan Headers 3 VREG 2 5 V Memory Standby Memory VREG 1 25 V Memory VVT VREG ATX P...

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