78
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
1. Route the TDI signal between the ITP700FLEX connector and the Intel Pentium M/Celeron M
processor. A 150-
Ω
±5 percent pull-up to VCCP (1.05 V) should be placed within ± 300 ps of
the TDI pin.
2. Route the TMS signal between ITP700FLEX connector and the Intel Pentium M/Celeron M
processor. A 39.2-
Ω
±1 percent pull-up to VCCP should be placed within ± 200 ps of the
ITP700FLEX connector pin.
3. Route the TRST# signal between ITP700FLEX connector and the Intel Pentium M/Celeron M
processor. A 510
Ω
to 680
Ω
± 5 percent pull-down to ground should be placed on TRST#.
Placement of the pull-down resistor is not critical. Avoid having any trace stub from the
TRST# signal line to the termination resistor.
4. Route the TCK signal from the ITP700FLEX connector’s TCK pin to the Intel Pentium
M/Celeron M processor’s TCK pin and then fork back from the Pentium M processor TCK pin
and route back to ITP700FLEX connector’s FBO pin. A 27.4
Ω
± 1 percent pull-down to
ground should be placed within ± 200 ps of the ITP700FLEX connector pin.
5. Route the TDO signal from the Intel Pentium M/Celeron M processor to a 54.9
Ω
± 1 percent
pull-up resistor to VCCP that should be placed close to ITP700FLEX connector’s TDO pin.
Then insert a 22.6
Ω
± 1 percent series resistor to connect the 54.9
Ω
pull-up and ‘TDOITP’
). Limit the L1 segment length of the TDOITP net to less than 1.0 inch.
The Intel Pentium M/Celeron M processor drives the BPM[4:0]# signals to the ITP700FLEX at a
100 MHz clock rate. Route the BPM[4:0]# as a Zo=55
Ω
point-to-point transmission line
connection between the processor and the ITP700FLEX connector. Connect the ITP700FLEX
Figure 36. ITP700FLEX Debug Port Signals
L8
L6
L7
L3
L2
L4
L1
L5
PREQ#
BPM[3:0]#
BPM[5:0]#
BPM[3:0]#
BPM[4]#
PRDY#
VCC
DBR#
RESET#
RESET#
RESET#
CPURESET#
ITPCLK[1:0]
BCLK[1:0]
CPUCLK[1:0]
GMCHCLK[1:0]
BCLK[1:0]
BCLKp
CK409
Intel
®
Pentium
®
M
Processor
Intel
®
855GME
Chipset
54.9
1%
1.05 v
22.6
1%
BPM[5]#
RESETITP#
240
5%
BCLKn
1.05 v
VTT
0.1u
F
VTT
150
5%
TDI
1.05 v
TDI
TDI
TDI
39.2
1%
TMS
1.05 v
TMS
TMS
TMS
680
5%
TRST#
TRST#
TRST#
TRST#
27.4
1%
TCK
TCK
TC
K
TCK
54.9
TDOITP
1.05 v
TDO
TDO
22.6
1%
TDO
FBO
FBO
FBO
VTAP
240
5%
VCC
DBA#
DBR
#
DBA
#
Summary of Contents for 6300ESB ICH
Page 24: ...24 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Introduction...
Page 102: ...102 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide...
Page 122: ...122 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide...
Page 190: ...190 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Hub Interface...
Page 318: ...318 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist...