Intel 6300ESB ICH, Design Manual

Page: 120 / 320

120
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
The ATX spec does not specify a minimum pulse width on PS_ON de-assertion; power supplies
must be able to handle any pulse width. This issue may affect any power supply (beyond ATX)
with similar PS_ON circuitry. Due to variance in the decay of the core power rails per platform, a
single board or chipset silicon fix would be non-deterministic (may not solve the issue in all cases).
The platform designer must ensure that the power supply used with the platform is not affected by
this issue.
4.8.6 Intel
®
6300ESB Analog Power Delivery
Ensure the 5 V analog plane used by AC ‘97 Audio is provided through a proper audio voltage
regulator (
Figure 63 ).
4.8.7 Intel
®
6300ESB Standby Power Distribution
To avoid radiated or conducted noise being coupling into the 6300ESB through the resume wells,
the standby power rails (V5REF_Sus & VccSus3_3) should be implemented using planes rather
than traces. The planes will have the capability to absorb the noise where a trace would serve as
antennae
4.8.8 Intel
®
6300ESB Power Consumption
Refer to the Intel
®
6300ESB I/O Controller Hub Datasheet for power consumption information.
4.8.9 Intel
®
6300ESB Decoupling Recommendations
The 6300ESB is capable of generating large current swings when switching between logic high and
logic low. This condition may cause the component voltage rails to drop below specified limits. To
avoid this type of situation, ensure that the appropriate amount of bulk capacitance is added in
parallel to the voltage input pins. It is recommended that the developer use the amount of
decoupling capacitors specified in
Table 26 to ensure the component maintains stable supply
voltages. Place the capacitors as close to the package as possible (100 mils nominal). Rotate caps
that sit over power planes so that the loop inductance is minimized. The basic theory for
minimizing loop inductance is to consider which voltage is on layer two (power or ground) and
spin the decoupling cap with the opposite voltage towards the BGA (Ball Grid Array). This greatly
minimizes the total loop inductance. It is recommended that for prototype board designs the
designer include pads for extra power plane decoupling caps.