Intel 6300ESB ICH, Design Manual

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Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
System Memory Design Guidelines (DDR-SDRAM)
5.4.5.4 Control Group Package Length Table
The package length data in the Table 37 shall be used to match the overall length of each command
signal to its associated clock reference length.
Note: Due to the relatively small variance in package length and adequate timing margins it is acceptable
to use a fixed 500 mil nominal package length for all control signals, thereby reducing the
complexity of the motherboard length calculations.
5.4.6 Command Signals – SMA[12:6,3,0], SBA[1:0],
SRAS#, SCAS#, SWE#
The 82855GME command signals, SMA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, and SWE#, are
clocked into the DDR SDRAMs using the clock signals SCK[5:0]/SCK[5:0]#. The GMCH drives
the command and clock signals together, with the clocks crossing in the valid command window.
The command signal group is supported by a daisy-chain topology.
5.4.6.1 Command Signal Routing Topology
The command signal routing shall transition from an external layer to an internal signal layer under
the GMCH. Keep the same internal layer until transitioning to an external layer immediately prior
to connecting the DIMM0 connector pad. At the via transition for DIMM0, continue the signal
route on the same internal layer until transitioning back out to an external layer to connect to the
pad of DIMM1. After DIMM1, transition to the same internal layer or stay on the external layer
and route the signal to Rt.
Intel suggests that the parallel termination (Rt) be placed on both sides of the board to simplify
routing and minimize trace lengths. All internal and external signals shall be ground referenced to
keep the path of the return current continuous.
Resistor packs are acceptable for the parallel command termination resistors but command signals
cannot be placed within the same R-packs as data, strobe, or control signals.
Figure 71 and
Table 38 present the recommended topology and layout routing guidelines for the DDR-SDRAM
command signals routing to DIMM0 and DIMM1.
Table 37. Control Group Package Lengths
Signal Pin Number Package Length (mils)
SCS[0]# AD23 502
SCS[1]# AD26 659
SCS[2]# AC22 544
SCS[3]# AC25 612
SCKE[0] AC7 443
SCKE[1] AB7 389
SCKE[2] AC9 386
SCKE[3] AC10 376