Intel 6300ESB ICH, Design Manual

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Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
20
Revision History
Date Revision Description
January 2007 006 Updated Table 2., "Reference Documents" .
October 2005 005
-Added additional acronyms to the terminology table.
-Clarified feature listings to accurately reflect latest supported features and products.
-Added descriptions of processors currently supported by the 855GME.
-Updated related documents references with current URLs.
-Added additional references to reflect document changes/additions.
-Revised stackup description in Chapter 3 to make sense.
-Fixed control signal to DIMM mapping.
-Added clarification on HSYNC/VSYNC isolation requirements.
-Added chapter for AGP design guidelines.
-Updated Section 6.2 references to 18bit LVDS support.
-Cleaned up formatting of Table 50 (LVDS Package Lengths).
-Replaced Section 6.3.1 subsections with Table 51 for readability.
-Added DVO to AGP pin mapping section (Section 6.3.1.1).
-Small consistency changes made throughout the document.
-Corrected references to PWRGOOD: Changed table 10 (section 4.1.5) to say AND gate, edited
section 4.1.5.4 to remove 6300ESB and replace with AND gate Figure will be updated as well,
changed reference to 6300ESB in schematics checklist and layout checklist to AND gate.
-Deleted duplicate copy of lntel
®
6300ESB power delivery figure in section 4.8.
-Added Standby power distribution section for lntel
®
6300ESB.
-Deleted section 4.8.8 (lntel
®
6300ESB power estimates) and added note.
-Change decoupling table for lntel
®
6300ESB to match DG insert rev 1.6.
-Deleted section 4.9 Thermal Design power and added note.
-Deleted superfluous transient response background information.
-Cleaned up Hub Interface chapter 8 deleted conflicting info etc.
-Updated all lntel
®
6300ESB information in chapter 9 to match the DG insert rev 1.6: Layout and
routing, FWH, GPIO and Power managment.
-Updated table 104 with 855GME spec update change (package lengths) from November 2004
revision.
-Updated Chapter 12 with all lntel
®
6300ESB recommendations to match DG insert rev 1.6.
-Updated chapter 13 with all lntel
®
6300ESB layout recommendations to match DG insert rev 1.6.
November 2004 004 Updated sections 8 and 11 with new Intel
®
6300ESB information.
August 2004 003 Added support for Intel
®
Pentium
®
M Low Voltage 738 Processor.
June 2004 002 Updated with support for the Intel
®
Pentium
®
M Processor on 90 nm process with 2 MB L2 cache
January 2004 001 Initial public release of this document.