Intel 6300ESB ICH, Design Manual

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January 2007 159
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Integrated Graphics Display Port
6.2.1 Length Matching Constraints
The routing guidelines presented in the following subsections define the recommended routing
topologies, trace width and spacing geometries, and absolute minimum and maximum routed
lengths for each signal group. These recommendations are provided to achieve optimal SI and
timing. In addition to the absolute length limits provided, more restrictive length matching
requirements are also provided. The additional requirements further restrict the minimum to
maximum length range of each signal group with respect to clock strobe, within the overall
boundaries defined in the guideline tables, as required to ensure adequate timing margins. These
secondary constraints are referred to as length matching constraints. The amount of minimum to
maximum length variance allowed for each group around the clock strobe reference length varies
from signal group to signal group depending on the amount of timing variation that may be
tolerated. Refer to
Table 45 for LVDS length matching requirements.
Each LVDS channel is length matched to the LVDS strobe signals. The strobes on a given channel
are matched to within ± 25 mils of the target length.
6.2.1.1 Package Length Compensation
As mentioned in Section 6.2.1 , all length matching is done from GMCH die-pad to LVDS
connector pin. The reason for this is to compensate for the package length variation across each
signal group in order to minimize timing variance. The GMCH does not equalize package lengths
internally as some previous GMCH components have, and therefore, the GMCH requires a length
matching process. Refer to
Table 47 for the Intel 855GME chipset LVDS package lengths
information.
Package length compensation shall not be confused with length matching as discussed in the
previous section. Length matching refers to constraints on the minimum and maximum length
bounds of a signal group based on clock length, whereas package length compensation refers to the
process of adjusting package length variance across a signal group. Of course, there is some
overlap in that both affect the target length of an individual signal. Intel recommends that the initial
route be completed based on the length matching formulas in conjunction with nominal package
lengths and that package length compensation be performed as secondary operation.
Table 45. LVDS Signal Trace Length Matching Requirements
Signal Group Data pair
Signal
Matching
Clock Strobes
associated with the
Channel
Strobe Matching
CHANNEL
A
IYAM0, IYAP0 ± 20 mils
ICLKAM, ICLKAP ± 20 mils
IYAM1, IYAP1 ± 20 mils
IYAM2, IYAP2 ± 20 mils
IYAM3, IYAP3 ± 20 mils
CHANNEL
B
IYBM0, IYBP0 ± 20 mils
ICLKAM, ICLKAP ± 20 mils
IYBM1, IYBP1 ± 20 mils
IYBM2, IYBP2 ± 20 mils
IYBM3, IYBP3 ± 20 mils
NOTE: All length matching formulas are based on GMCH die-pad to LVDS connector pin total length.
Package length tables are provided for all signals in order to facilitate this pad-to-pin matching.