January 2007
303
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Layout Checklist
RESET#
•
When ITP700 Is Used:
•
Fork out this signal from GMCH (
do not
T-split) and route to CPU and to Rtt/Rs
termination network placed near
ITP700FLEX debug connector.
•
Complete routing by connecting Rs to the
ITP700FLEX connector, limiting trace length
to less than 0.5 inches (L3).
•
Rtt is pulled-up to VCCP and should be
placed right next to Rs.
•
Trace length from GMCH to the Rtt/Rs
network near the debug connector should be
limited to less than 6 inches (L2).
•
The forked trace from the GMCH to the CPU
should be limited to a length range of 1 to 6
inches (L1).
•
ITP700FLEX debug operation requires
matching L2 + L3 - L1 length to within ± 50
ps of the length of the BPM[4:0] signals
detailed above.
•
Keep a minimum of 2:1 spacing in between
these signals and to other signals.
•
Reference these signals to ground planes
and avoid routing across power plane splits.
•
The number of routing layer transitions
should be minimized. When layout
constraints require a routing layer transition,
any such transition shall be accompanied
with ground stitching vias placed within 100
mils of the signal via with at least one ground
via for every two signals making a layer
transition.
•
Refer to
and
for details on
ITP700FLEX/RESET# routing
recommendations and resistive
network resistor values.
DBR#
•
When ITP700 Is Used:
•
Route to system reset logic with a pull-up
resistor to target system VCC.
•
Place pull-up resistor within 1 ns of the
ITP700FLEX debug connector.
TCK
•
When ITP700 Is Used:
•
Fork out this signal from the CPU (
do not
T-split) and route to the TCK pin and the
FBO pin of ITP700FLEX debug connector.
•
Parallel termination resistor to ground is
placed within ±200 ps of ITP700 connector.
•
Refer to
for details
on routing CPU TAP logic signals
for ITP700 debug operation.
TDI
•
When ITP700 Is Used:
•
Route between CPU and debug connector
pin.
•
Parallel termination resistor to VCCP is
placed within ±300 ps of CPU pin.
Table 148. Processor Layout Checklist (Sheet 4 of 7)
Checklist Items
Recommendations
Comments
Summary of Contents for 6300ESB ICH
Page 24: ...24 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Introduction...
Page 102: ...102 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide...
Page 122: ...122 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide...
Page 190: ...190 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Hub Interface...
Page 318: ...318 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist...
