Intel 6300ESB ICH, Design Manual

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January 2007 139
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
System Memory Design Guidelines (DDR-SDRAM)
External trace lengths shall be minimized. Intel suggests that the parallel termination be placed on
both sides of the board to simplify routing and minimize trace lengths. All internal and external
signals shall be ground reference to keep the path of return current continuous. Intel suggests that
all control signals be routed on the same internal layer.
Resistor packs are acceptable for the parallel (Rt) control termination resistors, but control signals
cannot be placed within the same R pack as the data or command signals. The table and diagrams
below depict the recommended topology and layout routing guidelines for the DDR-SDRAM
control signals.
5.4.5.1 Control Signal Routing Topology
Figure 69 depicts the control signal routing topology.
The control signals shall be routed using 2:1 trace spacing to trace width ratio for signals within the
DDR group, except clocks and strobes. Control signals shall be routed on inner layers with
minimized external trace lengths.
Figure 69. Control Signal Routing Topology
P1
V tt
D IM M 0 ,1 P A D
w
R t
L 2
M C H
P in
M C H
L 1