300
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Layout Checklist
Table 148. Processor Layout Checklist (Sheet 1 of 7)
Checklist Items
Recommendations
Comments
Intel
®
Pentium
®
M Processor Front Side Bus Interface Signals
A[31:3]#
ADSTB[1:0]#
DSTBN[3:0]#
DSTBP[3:0]#
DINV[3:0]#
D[63:0]#
REQ[4:0]#
•
Trace impedance = 55
Ω
± 15%.
•
Use strip-line routing, referencing ground
planes above and below the signal layer.
•
Route data strobes and data signals 4/12
with board trace length between 0.5 and 5.5
inches.
•
Use GMCH die-pad to processor pin length
for all length matching operations.
•
Length match data strobes of the same
group to within ± 25 mils of each other and to
the average length of their associated data
signal group.
•
Route all data signals as groups, on the
same layer, and balance within group ± 100
mils with respect to the associated strobes.
•
Route address strobes 4/12 and address
signals 4/8 with board trace length between
0.5 and 6.5 inches.
•
Trace length match address strobes to ± 200
mils of average length of their associated
address signals group.
•
AGTL+ Source Synchronous
Signals.
•
Refer to
for more
information.
ADS#
BNR#
BR0#
DBSY#
DRDY#
HIT#
HITM#
LOCK#
DPWR#
BPRI#
DEFER#
RS[2:0]#
TRDY#
•
Trace impedance = 55
Ω
± 15%.
•
Use strip-line routing, referencing solid
ground planes.
•
Route traces using 4/8 mils spacing with
board trace length between 1.0 and 6.5
inches.
•
Trace length matching is not required for
common clock signals.
•
Package length compensation is necessary
in determining minimum board trace length.
•
AGTL+ Common Clock Signals.
•
Refer to
for more
information.
RESET#
•
When ITP700 Is Not Used:
•
Trace impedance = 55
Ω
± 15%.
•
Use strip-line routing, referencing solid
ground planes.
•
Route traces using 4/8 mils spacing with
board trace length between 1.0 and 6.5
inches.
•
Trace length matching is not required for
common clock signals.
•
Package length compensation is necessary
in determining minimum board trace length.
•
Refer to ITP Section of this layout
checklist for treatment of RESET#
signal when implementing
ITP700FLEX debug port.
•
AGTL+ Common Clock Signal.
•
Refer to
for more
information.
Summary of Contents for 6300ESB ICH
Page 24: ...24 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Introduction...
Page 102: ...102 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide...
Page 122: ...122 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide...
Page 190: ...190 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Hub Interface...
Page 318: ...318 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist...
