Intel 6300ESB ICH, Design Manual

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Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Intel
®
Pentium
®
M/Celeron
®
M Processor FSB Design and Power Delivery Guidelines
For example, a length-matching requirement of ± 50 ps for routing on a strip-line (internal) layer
would correlate to a trace length whose tolerance are ± 278 mils of an associated trace. The signal
propagation time-to-distance relationship listed above is based on a single transmission line model
incorporating a typical stack-up. Thus, no other signals or traces are accounted for in such a model
and there is an assumption of zero coupling with other traces. Also, the recommended stack-up’s
parameter tolerances are not taken into account in the typical stack-up assumptions. Finally, in
cases that need to account for worst-case stack-up parameters and for even- or odd mode coupling,
new extractions from the stack-up model must be done to provide an accurate signal propagation
time-to-distance relationship.
4.1.2 Common Clock Signals
All common clock signals use an AGTL+ bus driver technology with on-die integrated GTL
termination resistors connected in a point-to-point, Zo = 55
Ω
, controlled impedance topology
between the Intel Pentium M/Celeron M Processor and the GMCH. No external termination is
needed on these signals. These signals operate at the Intel Pentium M/Celeron M Processor FSB
frequency of 100 MHz.
Common clock signals shall be routed on an internal layer while referencing solid ground planes.
Based on current simulation results, routing on internal layers allows for a minimum pin-to-pin
motherboard length of 1.0 inch and a maximum of 6.5 inches. Trace length matching for the
common clock signals is not required. For details on minimum motherboard trace length
requirements, refer to
Section 4.1.2.1 and Table 3 for more details. Intel recommends routing these
signals on the same internal layer for the entire length of the bus. When routing constraints require
routing of these signals with a transition to a different layer, a minimum of one ground stitching via
for every two signals shall be placed within 100 mils of the signal transition vias.
Routing of the common clock signals shall use 2:1 trace spacing to trace width. This implies a
minimum of 8 mils spacing (i.e., 12 mil minimum pitch) for a 4 mil trace width for routing on
internal layers. Practical cases of escape routing under the 82855GME or Intel Pentium M/Celeron
M Processor package outline and vicinity may not allow the implementation of 2:1 trace spacing
requirements. Although every attempt shall be made to maximize the signal spacing in these areas,
it is allowable to have 1:1 trace spacing underneath the GMCH and the Intel Pentium M/Celeron M
Processor package outlines and up to 200–300 mils outside the package outline.
Table 3 summarizes the list of common clock and key routing requirements. RESET#
(CPURESET# of GMCH) is also a common clock signal but requires a special treatment for the
case where an ITP700FLEX debug port is used. Refer to
Section 4.1.6 for further details.
Table 3. Intel
®
Pentium
®
M/Celeron
®
M Processor System Bus
Common Clock Signal Internal Layer Routing Guidelines (Sheet 1 of 2)
Signal Names
Transmission Line
Type
Total Trace Length
Nominal
Impedance
(
Ω
)
Width and
Spacing
(mils)
CPU GMCH
Min
(mils)
Max
(inches)
ADS# ADS# Strip-line 997 6.5 55 ± 15% 4 and 8
BNR# BNR# Strip-line 1298 6.5 55 ± 15% 4 and 8
BPRI# BPRI# Strip-line 1215 6.5 55 ± 15% 4 and 8
BR0# BR0# Strip-line 1411 6.5 55 ± 15% 4 and 8
† For topologies where an ITP700FLEX debug port is implemented, refer to Section 4.1.6 for RESET#
(CPURESET#) implementation details.