January 2007
93
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
A conceptual diagram of this V
CC-CORE
power delivery scheme is shown in
.
In this example, (option 4) bulk-decoupling 220 µF SP capacitors from V
CC-CORE
decoupling
option 4 are placed on the north side of the secondary side layer in the Intel Pentium M/Celeron M
processor V
CC-CORE
power delivery corridor. Notice the VRM feed point (sense resistor
connection) is on the positive terminal side of the 220 µF SP capacitors. Both V
CC-CORE
and
ground vias are used on both sides of the SP capacitors’ positive terminal side to reduce the
inductance of the capacitor connection as illustrated by the current flow loop area in
.
When the VR feed is on the negative side of the SP capacitors, both V
CC-CORE
and GND stitching
vias are needed on both the positive and negative terminals of the capacitor to reduce the effective
inductance of the capacitor.
Layers 1 (primary side layer), 3, 5, 6, and (secondary side layer) 8 are used for V
CC-CORE
current
feeding while referencing Layers 2, 4, and 7 (ground planes) with a small dielectric separation (see
). These layers are solid ground planes in the areas under the Intel Pentium M/Celeron M
processor package outline and where the decoupling capacitors are placed. This results in a
reduction in effective loop inductance. For the recommended layout examples shown in
and
, a low inductance value of ~41 pH is achieved.
Bulk decoupling capacitors respond too slowly to handle the fast current transients of the
processor. For this reason, 0805 mid-frequency decoupling capacitors are added on the primary and
secondary side. Some are placed under the package outline of the processor while the rest are
placed in the periphery of the processor along the AF signal row of the pin-map where a majority
of the V
CC-CORE
power pins are found. Four-mil power plane separation between the secondary
side power plane flood and Layer 7 ground while using the 0805 capacitors significantly reduces
the inductance of these capacitors. Results from a 3D field solver simulation suggest that an ESL of
600 pH per capacitor may be used to help achieve the specific layout style described in previous
sections. The ESL of the 0805 capacitors is a very critical parameter; the layout style shown in the
recommendation in a latter section shall be closely followed. To stress the importance of 0805
capacitors that result in an ESL of 600 pH, it may be compared to ~1.2 nH ESL for 1206 form
factor capacitors.
Figure 43. Intel
®
Pentium
®
M/Celeron
®
M Processor Core Power Delivery
and Decoupling Concept Example (Option #4)
SKT
VR
FEED
Rsens
e
35x10uF
0805
L1 PS
L2 GND
L3 Sig
L4 GND
L5 PWR
L6 Sig
L7 GND
L8 SS
9
6
8
9
3
PKG
VCC
-
CORE
4x220uF
SP Cap
VSS
Signals
+
-
+
South/Legacy Side
Intel
®
Pentium
®
M Processor Silicon Die
SKT
VR
FEED
Rsense
35x10uF
0805
L1 PS
L2 GND
L3 Sig
L4 GND
L5 PWR
L6 Sig
L7 GND
L8 SS
9
6
8
9
3
PKG
VCC
-
CORE
4x22
0uF
SP Cap
North Side
VSS
Signals
+
-
+
Summary of Contents for 6300ESB ICH
Page 24: ...24 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Introduction...
Page 102: ...102 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide...
Page 122: ...122 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide...
Page 190: ...190 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Hub Interface...
Page 318: ...318 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist...
