192
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Intel
®
6300ESB Design Guidelines
9.1.1.3
Serial ATA Trace Length Pair Matching
Serial ATA signal pair traces should be trace length matched. The difference of two line traces in a
differential pair should be restricted to below 10 mils.
9.1.1.4
Serial ATA Trace Length Guidelines
The length of the differential pairs (i.e., Tx pair and Rx pair) should be designed to within the
recommend values. The recommended length of the trace is from two to eight inches. When the
trace length of the differential pair is longer than recommended, the high-frequency differential
signal suffers significant signal attenuation and an increase in inter-symbol interference.
9.1.1.5
SATA BIAS Connections
It is recommended that the SATARBIASP and the SATARBIASN pins be shorted at the package
and the routed to one end of a 24.9
Ω
± 1% resistor to ground. Place the resistor within 500 mils of
the 6300ESB and avoid routing next to clock pins.
Figure 92.
Serial ATA Trace Spacing Recommendation
B1127-01
100
100
Distance in Mils
7.0
7.0
100
6.0
7.0
7.0 6.0
Clock/High-Speed
Periodic Signal
Differential
Pair
Low-speed
Non-Periodic
Signal
Differential
Pair
Table 72.
SATA Routing Summary
Differential
Trace
Impedance
SATA Routing Requirements
Trace Length
SATA Signal Length Matching
79.3
Ω
± 15%
7 mil width, 6 mil spacing
(Based on stackup described in
2-8 inches
Length mismatch between signals
in a data pair should be no more 10
mils.
Summary of Contents for 6300ESB ICH
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