Intel 6300ESB ICH, Design Manual

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Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Integrated Graphics Display Port
6.3.2.2 Package Length Compensation
As mentioned in Section 6.3.2.1 , all length matching is done from GMCH die-pad to DVO
connector pin. The reason for this is to compensate for the package length variation across each
signal group in order to minimize timing variance. The GMCH does not equalize package lengths
internally as some previous GMCH components have, and therefore, the GMCH requires a length
matching process. Refer to
Table 52 for the DVOB package lengths information and refer to
Table 53 for DVOC package lengths information.
Package length compensation shall not be confused with length matching as discussed in the
previous section. Length matching refers to constraints on the minimum and maximum length
bounds of a signal group based on clock length, whereas package length compensation refers to the
process of adjusting out package length variance across a signal group. There is of course some
overlap in that both affect the target length of an individual signal. Intel recommends that the initial
route be completed based on the length matching formulas in conjunction with nominal package
lengths and that package length compensation be performed as secondary operation.
Table 50. DVO Interface Trace Length Mismatch Requirements
Data Group
Signal Matching to
Strobe Clock
DVO Clock Strobes
Associated With the
Group
Clock Strobe Matching Notes
DVOBD [11:0] ±100 mils DVOBCLK[1:0] ± 10 mils 1 , 2
DVOCD [11:0] ±100 mils DVOCCLK[1:0] ± 10 mils 1 , 2
NOTES:
1. Data signals of the same group shall be trace length matched to the clock within ± 100 mil including
package lengths.
2. All length matching formulas are based on GMCH die-pad to DVO device pin total length. Package
length tables are provided for all signals to facilitate this pad-to-pin matching.