Intel 6300ESB ICH, Design Manual

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January 2007 255
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Platform Clock Routing Guidelines
11.2.3 CLK33 Clock Group
The 33 MHz clocks are series terminated and routed point-to point on the motherboard with
dedicated buffers for each of the loads. These clocks are length tuned to match the CLK66 clocks,
however, they are out of phase due to an internal phase delay in the CK409.
Figure 140 depicts the
CLK33 group topology. Table 108 presents the CLK33 clock group routing constraints.
Figure 140. CLK33 Group Topology
Table 108. CLK33 Clock Group Routing Constraints
Parameter Definition
Class Name CLK33
Class Type Individual Nets
Topology Series Terminated Point-to-Point
Reference Plane Ground Referenced
Single Ended Trace Impedance (Zo) 55
Ω
±15%
Nominal Inner Layer Trace Width 4.0 mils
Nominal Outer Layer Trace Width 5.0 mils (pin escapes only)
Minimum Spacing (See exceptions below.) 20 mils
Serpentine Spacing 20 mils
Maximum Via Count 4
Series Termination Resistor Value 33
Ω
±5%
Trace Length Limits – L1 Up to 500 mils
Trace Length Limits – L2 4.0” to 8.5”
Total Length Range – L1 + L2 CLK66 Length
Length Matching Required Yes (Pin to Pin)
Clock to Clock Matching ±100 mils
CLK33 to CLK33 to CLK66
Breakout Region Exceptions 5 mil trace with 5 mil space on outers
4 mil trace with 4 mil space in inners
Maximum breakout length is 0.3”
L1
Rs
CK409
Intel
®
6300ESB
SIO, FWH
L2