Intel 6300ESB ICH, Design Manual

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266
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Schematic Checklist Summary
IERR#
56
Ω
pull-up to
VCCP
IERR# is a 1.05 V signal.
Voltage translation logic and/or
series resistor may be required if
used.
INIT#
R1 = 1.3 K
Ω
R2 = 330
Ω
Rs = 330
Ω
Point-to-point connection to the
6300ESB (INIT# signal). Voltage
translation circuit is required if
connecting to FWH. Signal is T-
split from the 6300ESB to FWH.
Refer to Figure 148 .
IGNNE#
Point-to-point connection to the
6300ESB (IGNNE# signal).
LINT0
Point-to-point connection to the
6300ESB (INTR signal).
LINT1
Point-to-point connection to the
6300ESB (NMI signal).
PROCHOT#
56
Ω
pull up to
VCCP
R1 = 1.3 K
Ω
R2 = 330
Ω
Rs = 330
Ω
PROCHOT# is a VCCP signal.
Voltage translation logic may be
required if used.
When Voltage Translation is
Required: Driver isolation
resistor (Rs) shall be placed at
the beginning of the T-split to the
system receiver.
Refer to Figure 149 .
PSI#
May be left as NC, if not used for
IMVP.
PWRGOOD
330
Ω
pull-up to
VCCP
Point-to-point connection to an
output of an AND gate (AND of
PWRGD_3V and
CPU_VR_PWRGD) with resistor
placed by the processor.
RESET#
220
Ω
± 5%
pull-up to VCCP
WHEN USING
ITP700FLEX
22.6
Ω
± 1%
from pull-up
to
ITP700FLEX
When ITP700FLEX is Not
Used: Point-to-point connection
to GMCH (CPURST# signal).
When ITP700FLEX is Used:
RESET# connects from
processor to GMCH (CPURST#
signal) and then forks out to
ITP700 FLEX, with pull-up and
series damping resistor placed
next to ITP.
SLP#
Point-to-point connection to the
6300ESB (CPUSLP# signal).
SMI#
Point-to-point connection to the
6300ESB (SMI# signal).
STPCLK#
Point-to-point connection to the
6300ESB (STPCLK# signal).
Table 115. Connection Recommendations (Sheet 2 of 3)
Pin Name
System
Pull-up/Pull-down
Series
Termination
Voltage
Translation
Notes
√