302
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Layout Checklist
IGNNE#
LINT0/INTR
LINT1/NMI
SMI#
SLP#
A20M#
STPCLK#
•
May be routed as strip-line or micro-strip
with trace impedance = 55
Ω
± 15%.
•
Implement a point-to-point connection
between the 6300ESB and CPU, trace
length range between 0.5 and 12 inches.
•
No additional components are necessary for
this topology.
•
Asynchronous CMOS Input
Signals.
•
Refer to Topology 2B in
.
INIT#
•
May be routed as strip-line or micro-strip with
trace impedance = 55
Ω
± 15%.
•
Route signal point-to-point between the
6300ESB and CPU, trace length range
between 0.5 and 12 inches.
•
Voltage level translation is required from the
6300ESB INIT# pin to FWH.
•
Place series resistor Rs at the beginning of
trace T-split and within 3 inches from Q1.
•
Asynchronous CMOS Input
Signal.
•
Refer to Topology 3 in
for resistor values
and trace length
recommendations.
•
Refer also to
for
more details on voltage translation
recommendations.
•
The Intel customer reference
board makes use of an optional
alternative circuit for FWH voltage
translation. Refer to schematic
appendix.
Processor In Target Probe (ITP) Signals for ITP700FLEX Debug Port
BPM[3:0]#
PRDY#
PREQ#
•
Route as a point-to-point transmission line
connections from CPU pins to the
ITP700FLEX connector via Zo = 55
Ω
± 15%
traces. Limit trace length to shorter than 6
inches.
ITP700
to
CPU
BPM[3:0]#
BPM[3:0]#
BPM4#
PRDY#
BPM5#
PREQ#
•
Length match to each other within ± 50 ps.
•
These signals also must be length matched
to the net lengths of the RESET# signal
within ± 50 ps, as detailed in
.
•
Keep a minimum of 2:1 spacing in between
these signals and to other signals.
•
Reference these signals to ground planes
and avoid routing across power plane splits.
•
The number of routing layer transitions
should be minimized. When layout
constraints require a routing layer transition,
any such transition shall be accompanied
with ground stitching vias placed within 100
mils of the signal via with at least one ground
via for every two signals making a layer
transition.
•
Refer to
for important
design considerations when
implementing ITP700FLEX.
•
Refer to
for details
on signal propagation time to
distance relationships for the
length matching requirements
shown in this table as periods of
time.
•
for default
strapping and placement when
ITP debug port is not
implemented.
Table 148. Processor Layout Checklist (Sheet 3 of 7)
Checklist Items
Recommendations
Comments
Summary of Contents for 6300ESB ICH
Page 24: ...24 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Introduction...
Page 102: ...102 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide...
Page 122: ...122 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide...
Page 190: ...190 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Hub Interface...
Page 318: ...318 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist...
