Intel 6300ESB ICH, Design Manual

Page: 109 / 320

January 2007 109
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
4.8.1.2 DDR SDRAM VDD Decoupling
Discontinuities in the DDR signal return paths occur when the signals transition between the
motherboard and the DIMMs. To account for this ground to 2.5 V discontinuity, a minimum of nine
0603 form factor 0.1 µF high-frequency bypass capacitors is required between the DIMMs to help
minimize any anticipated return path discontinuities that shall be created. The capacitors shall be
distributed as evenly as possible between the two DIMMs.
•
Wide ground trace from each capacitor shall be connect to a via that transitions to the ground
plane. Each ground via shall be placed as close to the ground pad as possible.
•
Wide 2.5 V trace from each capacitor shall connect to a via that transitions to the 2.5 V copper
flood. Each via shall be placed as close to the capacitor pad as possible. Each capacitor pad
shall also connect to the closest 2.5 V DIMM pin on either the first or second DIMM
connector with a wide trace.
•
The DDR DIMMs also require bulk decoupling in addition to what is required by the GMCH.
Place a minimum of four 100-150 µF capacitors near the DIMM connectors.
4.8.1.3 DDR VTT Decoupling Placement and Layout Guidelines
The VTT termination rail must be decoupled using high-speed bypass capacitors, one 0603 form
factor, 0.1 µF capacitor per two DDR signals. They must be placed no more than 100 mils from the
termination resistors.
•
A VTT copper flood must be used. The decoupling capacitors must be spread out across the
termination rail so that all the parallel termination resistors are near high-frequency capacitors.
•
Each capacitor ground via shall be as close to the capacitor pad as possible, within 25 mils
with as thick a trace as possible.
•
Place one 4.7 µF ceramic capacitor on each end of the VTT termination rail, and place one
4.7 µF ceramic capacitor near the center of the termination rail. The power end of these
capacitors must connect directly to the VTT termination rail and the ground end is connected
to ground.
•
For low-frequency bulk decoupling at the VTT termination rail, evenly place four 470 µF
capacitors.
4.8.2 DDR Memory Power Delivery Design Guidelines
The focus of these GMCH guidelines is to minimize signal integrity problems and improve power
delivery to the GMCH system memory interface and the DDR memory DIMMs. This section
discusses the DDR memory system voltage and current requirements as determined at publishing
of this document. This document is not the original source for these specifications.
Figure 52
depicts the implementation of 2.5 V, 1.25 V and SMVREF on the CRB only as an example. It is the
responsibility of the system designer to ensure that the power requirements for the DDR and
GMCH are met. Refer to the following documents for the latest details on voltage and current
requirements found in this design guide.
•
JEDEC Standard, JESD79, Double Data Rate (DDR) SDRAM Specification
•
JEDEC 184-Pin Unbuffered DDR DIMM Specification
•
Intel 855GM/855GME Chipset (GMCH) Datasheet