Intel 6300ESB ICH, Design Manual

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Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
4.1.7 Pentium
®
M/Celeron
®
M Processor and Intel 855GME
Chipset GMCH (82855GME) Host Clock Signals
Figure 26 illustrates Intel Pentium M/Celeron M processor and 82855GME host clock signal
routing. Both the Intel Pentium M/Celeron M processor and the GMCH’s BCLK[1:0] signals are
initially routed from the CK409 clock generator on Layer 3. In the recommended routing example
(
Figure 26 ) secondary side layer routing of BCLK[1:0] is 507 mils long. To meet length-matching
requirements between the Intel Pentium M/Celeron M processor and GMCH’s BCLK[1:0] signals,
a similar transition from Layer 3 to the secondary side layer is done next to the Intel 855GME
chipset package outline. Routing of the GMCH’s BCLK[1:0] signals on the secondary side is also
trace tuned to 507 mils. BCLK[1:0] layer transition vias are accompanied by GND stitching vias.
For similar reasons, routing for the ITP interposer’s BCLK[1:0] signals also transition from Layer
3 to the secondary side layer and have 507-mil long traces on this layer. Throughout the routing
length on Layer 3, BCLK[1:0] signals shall reference a solid GND plane on Layer 2 and Layer 4 as
shown in
Figure 11 .
When a system supports either the onboard ITP700FLEX connector or ITP Interposer only,
differential host clock routing to either the ITP700FLEX connector or CPU socket (but not both) is
required.