Intel 6300ESB ICH, Design Manual

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January 2007 69
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
4.1.9 AGTL+ I/O Buffer Compensation
The Intel Pentium M/Celeron M processor has four pins, COMP[3:0], and the GMCH has two pins,
HRCOMP[1:0], that require compensation resistors to adjust the AGTL+ I/O buffer characteristics
to specific board and operating environment characteristics. The GMCH requires two special
reference voltage generation circuits to pins HSWNG[1:0] for the same purpose described above.
Refer to the Intel Pentium
®
M Processor Datasheet, Intel Celeron
®
M Datasheet, Intel Pentium
®
M Processor on 90nm Process with 2MB L2 Cache Datasheet and Intel
®
855GM/855GME Chipset
(GMCH) Datasheet for details on resistive compensation.
4.1.9.1 Pentium
®
M/Celeron
®
M Processor AGTL+ I/O Buffer Compensation
For the Intel Pentium M/Celeron M processor, the COMP[2] and COMP[0] pins (see Figure 29 )
each must be pulled-down to ground with 27.4
Ω
± 1% resistors and shall be connected to the Intel
Pentium M/Celeron M processor with a Zo = 27.4
Ω
trace that is less than 0.5 inches from the
processor pins. The COMP[3] and COMP[1] pins (see Figure 30 ) each must be pulled-down to
ground with 54.9
Ω
± 1% resistors and shall be connected to the Intel Pentium M/Celeron M
processor with a Zo = 55
Ω
trace that is less than 0.5 inches from the processor pins. COMP[3:0]
traces shall be at least 25 mils (> 50 mils preferred) away from any other toggling signal.
Figure 28. Intel
®
Pentium
®
M/Celeron
®
M Processor GTLREF Motherboard Layout
PRIMARY SIDE
Pin G1
Pin AG1
GTLREF
Zo = 55
Ω
<0.5”
R2
Pin E26
Banias
PRIMARY SIDE
Pin G1 Pin G1
Pin AG1
GTLREF
Zo =55
Ω
<0.5”
GTLREF
Zo =55
Ω
<0.5”
R1
R2
VCCP
Pin E26
Intel
®
Pentium
®
M
Processor