January 2007
75
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
4.2
Intel System Validation Debug Support
In any design, it is critical to enable industry-standard tools to allow for debugging a wide range of
issues that come up in the normal design cycle. In embedded designs, electrical/logic visibility is
very limited, often making progress on debugging such issues very time consuming. In some cases
progress it not possible without board re-design or extensive rework. Two topics in particular are
very important to general system debug capabilities.
4.2.1
ITP Support
4.2.1.1
Background/Justification
One key tool that is needed to debug BIOS, logic, signal integrity, general software, and general
hardware issues involving CPUs, chipsets, SIOs, PCI devices, and other hardware in a platform
design is the In Target Probe (ITP). The ITP is widely used by various validation, test, and debug
groups within Intel (as well as by third party BIOS vendors, OEMs, and other developers).
Note:
It is extremely important that any Intel Pentium M/Celeron M processor/Intel 855GME chipset-
based systems designed without ITP support may prevent assistance from various Intel validation,
test, and debug groups in debugging various issues. For this reason, it is critical that ITP support is
provided. This may be done with zero additional BOM cost and minimal layout/footprint costs.
The cost for not providing this support may be anywhere from none, if there are no blocking issues
found in the system design, to schedule slips of a month or more. The latter scenario represents the
time needed to spin a board design and required assembly time to add an ITP port when absolutely
required and other mechanical and routing issues prevent the use of an ITP interposer, if one exists.
4.2.1.2
Implementation
To minimize the ITP connector footprint, the ITP700Flex alternative is a better option for
embedded designs. The termination values do not need to be stuffed, thus zero additional BOM
cost. However, standard signal connection guidelines for the CPU’s TAP logic signals for the
non-ITP case still need to be followed. In other words, only the traces and component footprints
need to be added to the design, with all previous non-ITP guidelines followed otherwise. This way,
when ITP support is needed, the termination values and connector may be populated as needed for
debug support.
Note:
When the ITP700Flex footprint cannot be followed due to mechanical, routing, or footprint
reasons, it is acceptable to have a simple via grouping in lieu of the connector to allow for
‘blue-wiring’ of the ITP.
Summary of Contents for 6300ESB ICH
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Page 190: ...190 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Hub Interface...
Page 318: ...318 Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide Layout Checklist...
